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g04_lab03.sta.rpt
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g04_lab03.sta.rpt
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TimeQuest Timing Analyzer report for g04_lab03
Thu Apr 09 18:48:20 2015
Quartus II 64-Bit Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow Model Fmax Summary
7. Slow Model Setup Summary
8. Slow Model Hold Summary
9. Slow Model Recovery Summary
10. Slow Model Removal Summary
11. Slow Model Minimum Pulse Width Summary
12. Slow Model Minimum Pulse Width: 'altera_reserved_tck'
13. Slow Model Datasheet Report
14. Fast Model Setup Summary
15. Fast Model Hold Summary
16. Fast Model Recovery Summary
17. Fast Model Removal Summary
18. Fast Model Minimum Pulse Width Summary
19. Fast Model Minimum Pulse Width: 'altera_reserved_tck'
20. Fast Model Datasheet Report
21. Multicorner Timing Analysis Summary
22. Clock Transfers
23. Report TCCS
24. Report RSKM
25. Unconstrained Paths
26. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version ;
; Revision Name ; g04_lab03 ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C20F484C7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-----------------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 3.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 33.3% ;
+----------------------------+-------------+
+---------------------------------------------------+
; SDC File List ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+---------------+--------+--------------------------+
; g04_tempo.sdc ; OK ; Thu Apr 09 18:48:18 2015 ;
+---------------+--------+--------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+
; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { altera_reserved_tck } ;
+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+
---------------------------
; Slow Model Fmax Summary ;
---------------------------
No paths to report.
----------------------------
; Slow Model Setup Summary ;
----------------------------
No paths to report.
---------------------------
; Slow Model Hold Summary ;
---------------------------
No paths to report.
-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------------+
; Slow Model Minimum Pulse Width Summary ;
+---------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 97.531 ; 0.000 ;
+---------------------+--------+---------------+
+-------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'altera_reserved_tck' ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; 97.531 ; 100.000 ; 2.469 ; Port Rate ; altera_reserved_tck ; Rise ; altera_reserved_tck ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
-------------------------------
; Slow Model Datasheet Report ;
-------------------------------
Nothing to report.
----------------------------
; Fast Model Setup Summary ;
----------------------------
No paths to report.
---------------------------
; Fast Model Hold Summary ;
---------------------------
No paths to report.
-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Fast Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------------+
; Fast Model Minimum Pulse Width Summary ;
+---------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------------------+--------+---------------+
; altera_reserved_tck ; 97.778 ; 0.000 ;
+---------------------+--------+---------------+
+-------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'altera_reserved_tck' ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; 97.778 ; 100.000 ; 2.222 ; Port Rate ; altera_reserved_tck ; Rise ; altera_reserved_tck ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
-------------------------------
; Fast Model Datasheet Report ;
-------------------------------
Nothing to report.
+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+----------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+----------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; 97.531 ;
; altera_reserved_tck ; N/A ; N/A ; N/A ; N/A ; 97.531 ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
; altera_reserved_tck ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
+----------------------+-------+------+----------+---------+---------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 2 ; 2 ;
; Unconstrained Input Ports ; 22 ; 22 ;
; Unconstrained Input Port Paths ; 722 ; 722 ;
; Unconstrained Output Ports ; 68 ; 68 ;
; Unconstrained Output Port Paths ; 161 ; 161 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version
Info: Processing started: Thu Apr 09 18:48:12 2015
Info: Command: quartus_sta g04_lab03 -c g04_lab03
Info: qsta_default_script.tcl version: #1
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Evaluating HDL-embedded SDC commands
Info: Entity sld_hub
Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]
Info: set_clock_groups -asynchronous -group {altera_reserved_tck}
Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]
Info: set_clock_groups -asynchronous -group {altera_reserved_tck}
Warning: Overwriting existing clock: altera_reserved_tck
Info: Reading SDC File: 'g04_tempo.sdc'
Warning: At least one of the filters had some problems and could not be matched
Warning: clk could not be matched with a port
Warning: Ignored assignment: create_clock -name {} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}]
Warning: Argument <targets> is an empty collection
Warning: Node: Slowed_Altera_UP_Flash_Memory_UP_Core_Standalone:b2v_inst1|i_clock2 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: clk_50 was determined to be a clock but was found without an associated clock assignment.
Info: Analyzing Slow Model
Info: No fmax paths to report
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 97.531
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 97.531 0.000 altera_reserved_tck
Info: The selected device family is not supported by the report_metastability command.
Info: Report Minimum Pulse Width: Found 1 results (0 violated). Worst case slack is 97.531
Info: Targets: [get_clocks {altera_reserved_tck}]
Info: -nworst: 1
Info: -detail: full_path
Info: Path #1: slack is 97.531
Info: ===================================================================
Info: Node : altera_reserved_tck
Info: Clock : altera_reserved_tck
Info: Type : Port Rate
Info: Required Width : 2.469
Info: Actual Width : 100.000
Info: Slack : 97.531
Info: ===================================================================
Info:
Info: Analyzing Fast Model
Info: Started post-fitting delay annotation
Warning: Found 68 output pins without output pin load capacitance assignment
Info: Pin "I2C_SDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_RST_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "AUD_MCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "AUD_BCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "AUD_DACDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "AUD_DACLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "I2C_SCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FL_ADDR[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment4[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment4[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment4[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment4[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment4[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment4[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "segment4[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Node: Slowed_Altera_UP_Flash_Memory_UP_Core_Standalone:b2v_inst1|i_clock2 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: clk_50 was determined to be a clock but was found without an associated clock assignment.
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 97.778
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 97.778 0.000 altera_reserved_tck
Info: The selected device family is not supported by the report_metastability command.
Info: Report Minimum Pulse Width: Found 1 results (0 violated). Worst case slack is 97.778
Info: Targets: [get_clocks {altera_reserved_tck}]
Info: -nworst: 1
Info: -detail: full_path
Info: Path #1: slack is 97.778
Info: ===================================================================
Info: Node : altera_reserved_tck
Info: Clock : altera_reserved_tck
Info: Type : Port Rate
Info: Required Width : 2.222
Info: Actual Width : 100.000
Info: Slack : 97.778
Info: ===================================================================
Info:
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 10 warnings
Info: Peak virtual memory: 351 megabytes
Info: Processing ended: Thu Apr 09 18:48:20 2015
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:03