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Update Zicond instructions #452

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merged 4 commits into from
Feb 11, 2025
Merged

Update Zicond instructions #452

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9b2c6a6
complete czero instructions
jmawet Feb 1, 2025
8b87643
Merge branch 'riscv-software-src:main' into Zicond
jmawet Feb 1, 2025
f9550cd
Merge branch 'riscv-software-src:main' into Zicond
jmawet Feb 4, 2025
38633e9
syntax and style change
jmawet Feb 4, 2025
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18 changes: 15 additions & 3 deletions arch/inst/Zicond/czero.eqz.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,12 @@
$schema: "inst_schema.json#"
kind: instruction
name: czero.eqz
long_name: No synopsis available.
long_name: Conditional zero, if condition is equal to zero.
description: |
No description available.
If rs2 contains the value zero, this instruction writes the value zero to rd. Otherwise, this instruction
copies the contents of rs1 to rd.
This instruction carries a syntactic dependency from both rs1 and rs2 to rd. Furthermore, if the Zkt
extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2..
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definedBy: Zicond
assembly: xd, xs1, xs2
encoding:
Expand All @@ -24,12 +27,21 @@ access:
vu: always
data_independent_timing: false
operation(): |
XReg input1 = X[rs1];
XReg input2 = X[rs2];
XReg output = 0;

if(input2 != 0) {
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output = input1;
}

X[rd] = output;

sail(): |
{
let value = X(rs1);
let condition = X(rs2);
let result : xlenbits = if (condition != zeros()) then zeros()
let result : xlenbits = if (condition == zeros()) then zeros()
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else value;
X(rd) = result;
RETIRE_SUCCESS
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16 changes: 14 additions & 2 deletions arch/inst/Zicond/czero.nez.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,12 @@
$schema: "inst_schema.json#"
kind: instruction
name: czero.nez
long_name: No synopsis available.
long_name: Conditional zero, if condition is nonzero.
description: |
No description available.
If rs2 contains a nonzero value, this instruction writes the value zero to rd. Otherwise, this
instruction copies the contents of rs1 to rd.
This instruction carries a syntactic dependency from both rs1 and rs2 to rd. Furthermore, if the Zkt
extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2.
definedBy: Zicond
assembly: xd, xs1, xs2
encoding:
Expand All @@ -24,6 +27,15 @@ access:
vu: always
data_independent_timing: false
operation(): |
XReg input1 = X[rs1];
XReg input2 = X[rs2];
XReg output = 0;

if(input2 == 0) {
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output = input1;
}

X[rd] = output;

sail(): |
{
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