AR 2023-12-08

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Full Changelog since AR 2023-09-11: ar20230911...ar20231208
Full Changelog since AR 2023-09-14: ar20230914...ar20231208
Full Changelog since AR 2023-10-04: ar20231004...ar20231208
Full Changelog since AR 2023-10-12: ar20231012...ar20231208

What's Changed since AR 2023-10-12

• AR: Comment etrigger limited to 32 exceptions if XLEN=32 by @timsifive in #907
• AR: Comment itrigger limited to 32 ints if XLEN=32 by @timsifive in #906
• non-spec: Fix macro generation by @kr-sc in #902
• non-spec: The last field of a register was not printed by @en-sc in #908
• non-spec: Make register dump output more concise. by @timsifive in #909
• uncertain is updated when trigger fires. by @timsifive in #916
• Refer to "trigger registers" as "Trigger Module Registers" by @timsifive in #917
• Trigger CSRs provide access to underlying triggers. by @timsifive in #918
• CSR reset values apply to underlying triggers. by @timsifive in #920
• non-spec: Remove unnecessary parens. by @timsifive in #922
• Invalid addresses might not match. by @timsifive in #911

What's Changed since AR 2023-10-04

• AR: Update priority table from latest privspec by @timsifive in #897
• Add people with git PRs to credits. by @timsifive in #900
• AR: Clarify itrigger behavior. by @timsifive in #901
• AR: Clarify itrigger and trigger number translation by @timsifive in #903

Full Changelog: ar20231004...ar20231012

What's Changed since AR 2023-09-14

• Address review comments on debug_defines.h by @en-sc in #876
• Fix debugger examples: use transfer with write by @timsifive in #886
• AR: List which extensions were considered. by @timsifive in #881
• dscratch[01] are DXLEN bits wide. by @timsifive in #885
• AR: Clarify unimplemented Sdtrig. by @timsifive in #879
• AR: Clarify mcontext/hcontext. by @timsifive in #882
• AR: Remove Message Registers. by @timsifive in #878
• AR: tcontrol.mie applies to all traps, not just breakpoints by @timsifive in #880
• Clean up Makefile a little by @timsifive in #887
• AR: Clarify section/chapter in Sdext. by @timsifive in #895
• AR: Clarify why icount matches on every trap. by @timsifive in #896
• AR: Clarify what tmexttrigger.intctl is for by @timsifive in #898
• AR: Define mcontrol* triggers and multiple accesses by @timsifive in #883
• AR: Clarify triggers and multiple state changes by @timsifive in #899

What's Changed since AR 2023-09-11

• AR: Remove comment about privspec/CSR behavior by @timsifive in #874
• AR: Clarify what debuggers can assume about MRs by @timsifive in #875