Define the RV32-only medelegh CSR

src/images/bytefield/medeleg.adoc

@@ -7,11 +7,11 @@
 (def right-margin 100)
 (def boxes-per-row 32)
 
-(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}})
+(draw-box "63" {:span 16 :text-anchor "start" :borders {}})
 (draw-box "0" {:span 16 :text-anchor "end" :borders {}})
 
 (draw-box "Synchronous Exceptions" {:font-size 18 :span 18 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
 (draw-box (text "(WARL)" {:font-weight "bold"}) {:font-size 18 :span 14 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
 
-(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
-----
+(draw-box "64" {:font-size 24 :span 32 :borders {}})
+----

src/machine.adoc

@@ -1134,8 +1134,9 @@ appropriate level with the MRET instruction
 implementations can provide individual read/write bits within `medeleg`
 and `mideleg` to indicate that certain exceptions and interrupts should
 be processed directly by a lower privilege level. The machine exception
-delegation register (`medeleg`) and machine interrupt delegation
-register (`mideleg`) are MXLEN-bit read/write registers.
+delegation register (`medeleg`) is a 64-bit read/write register.
+The machine interrupt delegation register (`mideleg`) is an MXLEN-bit
+read/write register.
 
 In systems with S-mode, the `medeleg` and `mideleg` registers must
 exist, and setting a bit in `medeleg` or `mideleg` will delegate the
@@ -1203,6 +1204,10 @@ bit position equal to the value returned in the `mcause` register (i.e.,
 setting bit 8 allows user-mode environment calls to be delegated to a
 lower-privilege trap handler).
 
+When XLEN=32, `medelegh` is a 32-bit read/write register
+that aliases bits 63:32 of `medeleg`.
+Register `medelegh` does not exist when XLEN=64.
+
 .Machine Interrupt Delegation Register `mideleg`.
 include::images/bytefield/mideleg.adoc[]
 

src/priv-preface.adoc

@@ -36,6 +36,7 @@ version 1.12:
 
 * Defined the `misa`.V field to reflect that the V extension has been
 implemented.
+* Defined the RV32-only `medelegh` CSR.
 * Clarified semantics of explicit accesses to CSRs wider than XLEN bits.
 * Clarified that MXLEN≥SXLEN, and added the constraint that
 SXLEN≥UXLEN.