[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL

src/scalar-crypto.adoc

@@ -1,3 +1,4 @@
+[[crypto_scalar_instructions]]
 == Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1
 
 === Changelog

src/v-st-ext.adoc

@@ -228,6 +228,7 @@ will run. The `vill` bit in `vtype` should be checked after setting
 code path should be provided if it is not. Alternatively, a profile
 can mandate the minimum SEW at each LMUL setting.
 
+[[vector-register-grouping]]
 ===== Vector Register Grouping (`vlmul[2:0]`)
 
 Multiple vector registers can be grouped together, so that a single

src/vector-crypto.adoc

@@ -243,8 +243,13 @@ for vector crypto instructions.
 
 [[crypto-vector-instruction-constraints]]
 ==== Instruction Constraints
+
+All standard vector instruction constraints specified by RVV 1.0 apply to Vector Crypto instructions.
+In addition to those constraints a few additional specific constraints are introduced. 
+
 The following is a quick reference for the various constraints of specific Vector Crypto instructions.
 
+
 vl and vstart constraints::
 Since `vl` and `vstart` refer to elements, Vector Crypto instructions that use elements groups
 (See <<crypto-vector-element-groups>>) require that these values are an integer multiple of the
@@ -308,8 +313,13 @@ all other `SEW` values are _reserved_.
 
 |===
 
-Source/Destination overlap constraints::
-Some Vector Crypto instructions have overlap constraints. Encodings that violate these constraints are _reserved_.
+Vector/Scalar constraints::
+This specification defines new vector/scalar (.vs) instructions that uses *Scalar Element Groups*. The *Scalar Element Group* operand has `EMUL = ceil(EGW / VLEN)`.
+
+[NOTE]
+====
+Scalar element group operands do not need to be aligned to LMUL for any implementation with VLEN >= EGW.
+====
 
 In the case of the `.vs` instructions defined in this specification, `vs2` holds a 128-bit scalar element group.
 For implementations with `VLEN` ≥ 128, `vs2` refers to a single register. Thus, the `vd` register group must not
@@ -353,7 +363,6 @@ The Vector Crypto Extensions define Vector-Scalar instructions that are similar
 Vector Reduction Operations in that they get a scalar operand from a vector register. However, they differ
 in that they get a scalar element group
 (see <<crypto-vector-element-groups>>)
-// link:https://github.com/riscv/riscv-v-spec/blob/master/element_groups.adoc[RISC-V Vector Element Groups])
 from `vs2` and they return _vector_ results to `vd`, which is also a source vector operand.
 These Vector-Scalar crypto instructions also use the `.vs` suffix in their mnemonics.
 
@@ -482,7 +491,7 @@ on _any_ embedded (Zve*) or application ("V") base Vector Extension.
 All _cryptography-specific_ instructions defined in this Vector Crypto specification (i.e., those
 in <<zvkned>>, <<zvknh,Zvknh[ab]>>, <<Zvkg>>, <<Zvksed>> and <<zvksh>> but _not_ <<zvbb>>,<<zvkb>>, or <<zvbc>>) shall
 be executed with data-independent execution latency as defined in the
-link:https://github.com/riscv/riscv-crypto/releases/tag/v1.0.1-scalar[RISC-V Scalar Cryptography Extensions specification].
+<<#crypto_scalar_instructions,RISC-V Scalar Cryptography Extensions specification>>.
 It is important to note that the Vector Crypto instructions are independent of the
 implementation of the `Zkt` extension and do not require that `Zkt` is implemented.
 
@@ -998,7 +1007,7 @@ GCM/GMAC extension to enable high-performace SM4-GCM.
 
 The Zvkt extension requires all implemented instructions from the following list to be
 executed with data-independent execution latency as defined in the 
-link:https://github.com/riscv/riscv-crypto/releases/tag/v1.0.1-scalar[RISC-V Scalar Cryptography Extensions specification].
+<<#crypto_scalar_instructions,RISC-V Scalar Cryptography Extensions specification>>.
 
 Data-independent execution latency (DIEL) applies to all _data operands_ of an instruction, even those that are not a
 part of the body or that are inactive. However, DIEL does not apply