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Signed-off-by: Ravi Sahita <[email protected]> Signed-off-by: Ravi Sahita <[email protected]>
riscv · Dec 11, 2023 · 453ddb6 · 453ddb6
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Showing 2 changed files with 9 additions and 10 deletions.
diff --git a/chapter3.adoc b/chapter3.adoc
@@ -21,10 +21,10 @@ an illegal instruction exception.
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits:  6, name: 'SDID'},
+  {bits:  22, name: 'PPN (WARL)'},
   {bits:  2, name: 'WPRI'},
-  {bits:  2, name: 'Mode'},
-  {bits:  22, name: 'PPN'},
+  {bits:  6, name: 'SDID (WARL)'},
+  {bits:  2, name: 'Mode (WARL)'},
 ], config:{lanes: 1, hspace:1024}}
 ....
 
@@ -34,11 +34,10 @@ an illegal instruction exception.
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits:  6, name: 'SDID'},
-  {bits:  2, name: 'WPRI'},
-  {bits:  4, name: 'Mode'},
-  {bits:  44, name: 'PPN'},
-  {bits:  8, name: 'WPRI'},
+  {bits:  44, name: 'PPN (WARL)'},
+  {bits:  10, name: 'WPRI'},
+  {bits:  6, name: 'SDID (WARL)'},
+  {bits:  4, name: 'Mode (WARL)'},
 ], config:{lanes: 1, hspace:1024}}
 ....
 

diff --git a/header.adoc b/header.adoc
@@ -1,8 +1,8 @@
 [[header]]
 :description: RISC-V Supervisor Domains Access Protection
 :company: RISC-V.org
-:revdate: 7/2023
-:revnumber: 1.0
+:revdate: 12/2023
+:revnumber: 1.0.4
 :revremark: This document is in development. Assume everything can change. See http://riscv.org/spec-state for details.
 :url-riscv: http://riscv.org
 :doctype: book