update bit position of valid bit in MTTL3

Signed-off-by: Ravi Sahita <[email protected]>
riscv · Oct 15, 2024 · a9bb6f1 · a9bb6f1
1 parent 8447ac2
commit a9bb6f1
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/chapter4.adoc b/chapter4.adoc
@@ -59,8 +59,8 @@ The following MTT L3 entry accomodates a 56 bit PAW:
 ....
 {reg: [
   {bits:  44, name: 'MTTL2 PPN'},
-  {bits:  19, name: 'ZERO'},
   {bits:   1, name: 'VALID'},
+  {bits:  19, name: 'ZERO'},
 ], config:{lanes: 1, hspace:1024}}
 ....