Proposed changes to mttp CSR

[rsahita]

proposed changes to mttp CSR to reserve upper bits for expanded PA (future), and reduce SDID to 6 bits and reserve remaining bits

[gagachang]

Hello Ravi, may I know the rationale of reducing SDID to 6 bits?

[rsahita]

Hi @gagachang - we had not formally discussed the width of this field - given what we expect for usages, such as Confidential Computing, Keystone, various TEEs, VSM, pKVM etc, it seemed that a handful of supervisor domains would be reasonable, so 6 bits seemed apropos. (We can keep some bits reserved for future in the register as specified).

[ved-rivos]

Zero -> WPRI
MTTPPN -> PPN (since the CSR already says its MTT).

[rsahita]

@kasanovic any feedback on this change - please ack if none, then I can merge it.

[ved-rivos]

Should we organize the fields as: [MODE | SDID | WPRI | PPN]. Instead of splitting the reserved field into two group of bits make it one contiguous run of reserved bits between the MODE, SDID, and PPN fields.

[rsahita]

so the first WPRI bits are for other control bits if needed (like lock) and the second WPRI bits are for the PPN expansion (future)

[ved-rivos]

The other controls could be filled in the WPRI run of bits for future - growing towards right. The PPN would want to expand and grow towards left.

[rsahita]

ack

[kasanovic]

The format of the remaining fields should be dependent on mode setting, to leave the most flexibility for future enhancements. So the breakdown into SDID/PPN/WPRI should be mode-specific, and so we're only specifying this split for the modes we're proposing in this version of spec, not all possible values of mode field.

[kasanovic]

I see now there's already a sentence in spec saying what's in my last comment, so can ignore.

[kasanovic]

The PPN should be aligned in the LSBs just as with satp.

[rsahita]

updated per feedback

[ved-rivos]

The update defined it as [PPN, WPRI, SDID, MODE] instead of [MODE, SDID, WPRI, PPN].

[ved-rivos]

@rsahita The change needed is as follows (Changing lanes to 2 also improves the readability in the PDF)
For RV64:

{reg: [
  {bits:  44, name: 'PPN (WARL)'},
  {bits:  10, name: 'WPRI'},
  {bits:   6, name: 'SDID (WARL)'},
  {bits:   4, name: 'Mode (WARL)'},
], config:{lanes: 2, hspace:1024}}

For RV32:

{reg: [
  {bits:  22, name: 'PPN (WARL)'},
  {bits:   2, name: 'WPRI'},
  {bits:   6, name: 'SDID (WARL)'},
  {bits:   2, name: 'Mode (WARL)'},
], config:{lanes: 2, hspace:1024}}

[rsahita]

yes i noticed the error and had fixed it :-) - will update to improve readability per your comment (thanks)

[ved-rivos]

@rsahita another thing to fix is perhaps to remove "All sub-fields are WARL." since some subfields are not.