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smmtt updates per TG call on 4/30 #48
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Signed-off-by: Ravi Sahita <[email protected]>
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A good step forward. One thing is the name of the FENCE.MTT instruction - it might be probably more accurately named an MFENCE.SD instruction as it can be used without MTT tables in memory, and is only for M-mode.
Signed-off-by: Ravi Sahita <[email protected]>
Please see updated PR @kasanovic |
Co-authored-by: Ved Shanbhogue <[email protected]> Signed-off-by: Ravi Sahita <[email protected]>
Signed-off-by: Ravi Sahita <[email protected]>
Co-authored-by: Ved Shanbhogue <[email protected]> Signed-off-by: Ravi Sahita <[email protected]>
exceptions. The exception conditions for MTT are checked when the access | ||
to memory is performed. | ||
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=== Caching of MTT and Supervisor Domain Fence Instruction |
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This section is mostly redundant and covered by the MFENCE.SPA and MINVAL.SPA. Whether MTT is cached is microarchitectural. The last paragraph and the note preceeding that could be moved inline with these instructions description and rest of this section removed.
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i thought of keeping this section since it is in the normative Smmtt part of the spec. if anything is incorrect here we should fix it, but o/w it seems useful.
Co-authored-by: Ved Shanbhogue <[email protected]> Signed-off-by: Ravi Sahita <[email protected]>
Addressed opens discussed in the 4/30 TG call : https://lists.riscv.org/g/tech-smmtt/message/67
-Moved theory of operation of memory isolation (non-normative) to intro chapter 1
-Updated figure showing logical enforcement of MTT (hart and IO side accesses)
-Updated intro to extensions chapter 2
-Added clarification on SDID usage as local id, PMP usage
-Added description of MTT synchronization (was TBD)
-Fixed glossary errors