Correct signs and explicitly clarify MTTL2 table sizes

[grg-haas]

This change mainly clarifies the MTTL2 table sizes for various SMMTT modes and PAWs. As stated, it was unclear whether the specified table sizes apply when the PAW changes (i.e. Smmtt46[rw] has a table size of 2^(PAW-23), Smmtt34[rw] has a table size of 2^(PAW-22)) or when the RW mode changes (i.e. Smmtt46 and Smmtt34 have a table size of 2^(PAW-23), Smmtt46rw and Smmtt34rw have a table size of 2^(PAW-22)). Based on the diagrams later in the spec, I believe the latter interpretation is correct so lets make it explicit.

Also, the inequality signs for PAW specifications were incorrect so this commit fixes this as well

[grg-haas]

This actually brings up another issue, one which I think may be a bug in the spec. Consider that Smmtt34rw would have an MTTL2 of size 2^(34-22) = 4096 bytes, or exactly the size of a page. However, Smmtt34's MTTL2 would then have a size of 2^(34-23) = 2048 bytes, which is only half a page. It would then not actually always be possible to store the PPN of this MTTL2 table in the mttp register, since there are two half-pages per PPN. Should there be an extra line in the spec which indicates that MTTL2 should be at least page aligned?

[grg-haas]

I guess this also makes the following line fairly confusing: "In these modes, the lowest two bits of the physical page number (MTTPPN) in mttp always read as zeros". This would imply alignment of at least 16384 bytes? Also its unclear what specific modes "these modes" is referring to.

[rsahita]

thanks!