Added implementations of default callbacks for trace printing in risc…

…v_default_callbacks.c

Makefile

@@ -223,14 +223,7 @@ cloc:
 gcovr:
 	gcovr -r . --html --html-detail -o index.html
 
-c_preserve_fns=-c_preserve _set_Misa_C \
-  -c_preserve mem_write_callback_default \
-  -c_preserve mem_read_callback_default \
-  -c_preserve xreg_write_callback_default \
-  -c_preserve freg_write_callback_default \
-  -c_preserve csr_write_callback_default \
-  -c_preserve csr_read_callback_default \
-  -c_preserve vreg_write_callback_default
+c_preserve_fns=-c_preserve _set_Misa_C
 
 generated_definitions/c/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile
 	mkdir -p generated_definitions/c

c_emulator/riscv_default_callbacks.c

@@ -1,54 +1,85 @@
 #include "riscv_config.h"
+#include <stdlib.h>
 
-int zmem_write_callback_default(long unsigned int addr, long int width, lbits value);
-int zmem_read_callback_default(const char *type, long unsigned int addr,
-                               long int width, lbits value);
-int zxreg_write_callback_default(long unsigned int reg, long unsigned int value);
-int zfreg_write_callback_default(long unsigned int reg, long unsigned int value);
-int zcsr_write_callback_default(long unsigned int reg, long unsigned int value);
-int zcsr_read_callback_default(long unsigned int reg, long unsigned int value);
-int zvreg_write_callback_default(long unsigned int reg, lbits value);
 
-/* The model assumes that these functions do not change the state of the model.
+void zcsr_name_map_forwards(sail_string *rop, uint64_t);
+
+static uint8_t *get_lbits_data(lbits val) {
+  uint8_t *data = (uint8_t*)calloc(val.len, sizeof(uint8_t));
+  mpz_export(data, NULL, -1, 1, 0, 0, val.bits);
+  return data;
+} 
+
+/* Implementations of default callbacks for trace printing.
+ *
+ * The model assumes that these functions do not change the state of the model.
  */
 int mem_write_callback(uint64_t addr, uint64_t width, lbits value) {
-  if (config_print_mem_access)
-    zmem_write_callback_default(addr, width, value);
+  if (config_print_mem_access) {
+    char *lbits_data = get_lbits_data(value);
+    printf("mem[0x%lX] <- 0x", addr);
+    for (int i = width - 1; i >= 0; --i)
+      printf("%02hhX", lbits_data[i]);
+    printf("\n");
+    free(lbits_data);
+  }
 }
 
 int mem_read_callback(const char *type, uint64_t addr, uint64_t width,
                       lbits value)
 {
-  if (config_print_mem_access)
-    zmem_read_callback_default(type, addr, width, value);
+  if (config_print_mem_access) {
+    char *lbits_data = get_lbits_data(value);
+    printf("mem[%s,0x%lX] -> 0x", type, addr);
+    for (int i = width - 1; i >= 0; --i)
+      printf("%02hhX", lbits_data[i]);
+    printf("\n");
+    free(lbits_data);
+  }
 }
 
 int mem_exception_callback(uint64_t addr, uint64_t num_of_exception) { }
 
 int xreg_write_callback(unsigned reg, uint64_t value) { 
   if (config_print_reg)
-    zxreg_write_callback_default(reg, value);
+    printf("x%d <- 0x%.16lX\n", reg, value);
 }
 
 int freg_write_callback(unsigned reg, uint64_t value) {
   /* TODO: will only print bits; should we print in floating point format? */
   if (config_print_reg)
-    zfreg_write_callback_default(reg, value);
+    printf("f%d <- 0x%.16lX\n", reg, value);
 }
 
 int csr_write_callback(unsigned reg, uint64_t value) {
-  if (config_print_reg)
-    zcsr_write_callback_default(reg, value);
+  if (config_print_reg) {
+    sail_string csr_name;
+    CREATE(sail_string)(&csr_name);
+    zcsr_name_map_forwards(&csr_name, reg);
+    printf("csr %s <- 0x%.16lX (input: 0x%.16lX)\n", csr_name, value, value);
+    KILL(sail_string)(&csr_name);
+  }
 }
 
 int csr_read_callback(unsigned reg, uint64_t value) {
-  if (config_print_reg)
-    zcsr_read_callback_default(reg, value);
+  if (config_print_reg) {
+    sail_string csr_name;
+    CREATE(sail_string)(&csr_name);
+    zcsr_name_map_forwards(&csr_name, reg);
+    printf("csr %s -> 0x%lX\n", csr_name, value);
+    KILL(sail_string)(&csr_name);
+  }
 }
 
 int vreg_write_callback(unsigned reg, lbits value) {
-  if (config_print_reg)
-    zvreg_write_callback_default(reg, value);
+  if (config_print_reg) {
+    char *lbits_data = get_lbits_data(value);
+    printf("v%d <- ", reg);
+    for (int i = value.len - 1; i >= 0; --i)
+      printf("%02hhX", lbits_data[i]);
+    printf("\n");
+    free(lbits_data);
+  }
 }
 
 int pc_write_callback(uint64_t value) { }

model/riscv_csr_begin.sail

@@ -350,16 +350,3 @@ scattered function read_CSR
 val write_CSR : (csreg, xlenbits) -> xlenbits
 scattered function write_CSR
 
-
-/* Implementations of default callbacks for trace printing */
-
-val csr_write_callback_default : (csreg, xlenbits) -> unit
-function csr_write_callback_default (csr, value) = {
-  print_reg("csr " ^ csr_name_map(csr) ^ " <- " ^ BitStr(value) ^ " (input: " ^ BitStr(value) ^ ")")
-}
-
-val csr_read_callback_default : (csreg, xlenbits) -> unit
-function csr_read_callback_default (csr, value) = {
-  print_reg("csr " ^ csr_name_map(csr) ^ " -> " ^ BitStr(value))
-}
-

model/riscv_types.sail

@@ -426,27 +426,3 @@ val freg_write_callback = pure {c: "freg_write_callback"} : (regidx, flenbits) -
 val csr_write_callback = pure {c: "csr_write_callback"} : (csreg, xlenbits) -> unit
 val csr_read_callback = pure {c: "csr_read_callback"} : (csreg, xlenbits) -> unit
 
-/* Implementations of default callbacks for trace printing */
-
-val mem_write_callback_default : forall 'n, 0 < 'n <= max_mem_access . (/* addr */ xlenbits, /* width */ int('n), /* value */ bits(8 * 'n)) -> unit
-function mem_write_callback_default (addr, width, value) = {
-  print_mem("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(value))
-}
-
-val mem_read_callback_default : forall 'n, 0 < 'n <= max_mem_access . (/* access type */ string, /* addr */ xlenbits, /* width */ int('n), /* value */ bits(8 * 'n)) -> unit
-function mem_read_callback_default (t, addr, width, value) = {
-  print_mem("mem[" ^ t ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(value))
-}
-
-val xreg_write_callback_default : (regidx, xlenbits) -> unit
-function xreg_write_callback_default (reg, value) = {
-  print_reg("x" ^ dec_str(regidx_to_regno(reg)) ^ " <- " ^ BitStr(value))
-}
-
-val freg_write_callback_default : (regidx, flenbits) -> unit
-function freg_write_callback_default (reg, value) = {
-  /* todo: will only print bits; should we print in floating point format? */
-  print_reg("f" ^ dec_str(regidx_to_regno(reg)) ^ " <- " ^ BitStr(value))
-}
-
-

model/riscv_vreg_type.sail

@@ -153,12 +153,3 @@ enum vmlsop       = { VLM, VSM }
 
 val vreg_write_callback = pure {c: "vreg_write_callback"} : (regidx, vregtype) -> unit
 
-/* Implementations of default callbacks for trace printing */
-
-val vreg_write_callback_default : (regidx, vregtype) -> unit
-function vreg_write_callback_default (reg, value) = {
-  let VLEN = unsigned(vlenb) * 8;
-  assert(0 < VLEN & VLEN <= sizeof(vlenmax));
-  print_reg("v" ^ dec_str(regidx_to_regno(reg)) ^ " <- " ^ BitStr(value[VLEN - 1 .. 0]))
-}
-