[PPC/ARM] Update to Capstone v6/auto-sync (#3648)

ARM
- Updated ARM identifiers and API changes.
- Fixed shift amounts to be always decimal.
- Fixed incorrect usages of memory disponents.
- Fixed restoring of condition codes.
- Updated IDs for new ones.
- Fixed 8-byte stores.
- Added flag checking for MOV with shifts.
Capstone Integration
- Removed capstone-auto-sync subproject and replaced with next.
- Checked for NEON features.
- Used capstone-engine/capstone#2122 for better system operand support.
- Distinguished between 32 and 64-bit cc checks.
- Checked for CS API version >5.
- Checked for CS_NEXT_VERSION instead of CS_API_MAJOR.
- Fixed VSTn and VLDn instructions to use corrected memory operands.
- Excluded multiple instruction aliases that are no longer valid IDs.
- Used CS_NEXT_VERSION as include guard.
- Added CS v6 include guards.
- Added CS v6 support to branch conditions for Rzil.
- Added more CSv6 guards.
PPC
- Fixed: Compare instructions do not use the branch predicate.
- Fixed conditional and CTR checks.
- Fixed MTSPR and MFSPR instructions.
- Excluded more branch aliases no longer present in v6 from switch cases.
- Fixed incorrectly assigned variables.
- Fixed condition checks for branches.
- Used ITE for condition checks, to prevent unnecessary reads of CTR or CR.
- Fixed rzil tests with new semantics using register 0.
- Updated include guards for Capstone versions to use CS_NEXT_VERSION.
- Initialized spr_name to prevent uninitialized use.
- Used mem.offset register for CSv6.
- Always used real operand details.
- Used mem operand for DCBZ.
- Fixed tests that are semantically identical.
- Handled LI LIS alias.
- Fixed rzil tests (with simplified semantics).
- Fixed branch alias with new cond test method.
- Handled clrl. alias.
- Handled SL/SR alias.
- Fixed conditional branches in ESIL.
- Fixed possible multiplication result overflow.
- Added RZ_NONNULL.
- Added 0 register.
- Handled LIS alias.
- Fixed: Print crX reg name in CS v6.
- Handled all general branch instructions into a single case statement.
- Fixed no semantic issues in tests.
- Added newly discovered calls.
- Moved direction check to inline function.
- Added link of root cause for broken test.
- Added QPX support.
- Set Capstone next branch to latest commit.
- Fixed uninitialized warning.
- Set CS next branch to newest commit.

librz/analysis/arch/arm/arm_accessors32.h

@@ -17,9 +17,11 @@
 // s/index/base|reg/
 #define HASMEMINDEX(x)   (insn->detail->arm.operands[x].mem.index != ARM_REG_INVALID)
 #define ISMEMINDEXSUB(x) insn->detail->arm.operands[x].subtracted
-#define MEMDISP(x)       insn->detail->arm.operands[x].mem.disp
+#define MEMDISP(x)       (ISMEMINDEXSUB(x) ? -insn->detail->arm.operands[x].mem.disp : insn->detail->arm.operands[x].mem.disp)
+#define MEMDISP_BV(x)    (HASMEMINDEX(x) ? REG_VAL(insn->detail->arm.operands[x].mem.index) : U32(MEMDISP(x)))
 #define ISIMM(x)         (insn->detail->arm.operands[x].type == ARM_OP_IMM || insn->detail->arm.operands[x].type == ARM_OP_FP)
 #define ISREG(x)         (insn->detail->arm.operands[x].type == ARM_OP_REG)
+#define ISPSRFLAGS(x)    (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR)
 #define ISMEM(x)         (insn->detail->arm.operands[x].type == ARM_OP_MEM)
 #define ISFPIMM(x)       (insn->detail->arm.operands[x].type == ARM_OP_FP)
 
@@ -38,6 +40,7 @@
 	SHIFTTYPE(x) == ARM_SFT_RRX_REG)
 #define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value
 
-#define ISWRITEBACK32() insn->detail->arm.writeback
-#define ISPREINDEX32()  (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32())) || ((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32())))
-#define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32())))
+#define ISPOSTINDEX()   insn->detail->arm.post_index
+#define ISWRITEBACK32() insn->detail->writeback
+#define ISPREINDEX32()  (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())) || \
+	((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())))

librz/analysis/arch/arm/arm_cs.h

@@ -10,7 +10,10 @@
 RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb);
 RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn);
 
-RZ_IPI const char *rz_arm_cs_esil_prefix_cond(RzAnalysisOp *op, int cond_type);
+RZ_IPI bool rz_arm_cs_is_group_member(RZ_NONNULL const cs_insn *insn, arm_insn_group feature);
+
+RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCodes cond_type);
+RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);
 
 RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
 RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);