witlb|wsr

rizinorg · Nov 28, 2024 · 862fe9d · 862fe9d
1 parent 2d0b79e
commit 862fe9d
Show file tree

Hide file tree

Showing 2 changed files with 18 additions and 0 deletions.
diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -1344,6 +1344,15 @@ static RzAnalysisLiftedILOp op_wfr(XtensaContext *ctx) {
 	return SETG(REGN(0), V64(IREG(1)));
 }
 
+// TODO: datatlb
+static RzAnalysisLiftedILOp op_witlb(XtensaContext *ctx) {
+	return NOP();
+}
+
+static RzAnalysisLiftedILOp op_wsr(XtensaContext *ctx) {
+	return SETG(REGN(0), IREG(1));
+}
+
 #include <rz_il/rz_il_opbuilder_end.h>
 
 static const fn_analyze_op_il fn_tbl[] = {
@@ -1639,6 +1648,8 @@ static const fn_analyze_op_il fn_tbl[] = {
 	[XTENSA_INS_WDTLB] = op_wdtlb,
 	[XTENSA_INS_WER] = op_wer,
 	[XTENSA_INS_WFR] = op_wfr,
+	[XTENSA_INS_WITLB] = op_witlb,
+	[XTENSA_INS_WSR] = op_wsr,
 };
 
 void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -291,3 +291,10 @@ d "waiti 0xf" 007f00 0x0 nop
 d "wdtlb a1, a2" 10e250 0x0 nop
 d "wer a1, a2" 107240 0x0 nop
 d "wfr f1, a2" 5012fa 0x0 (set f1 (cast 64 false (var a2)))
+d "wsr a1, lend" 100113 0x0 (set a1 (var lend))
+d "wsr a1, lcount" 100213 0x0 (set a1 (var lcount))
+d "wsr a1, sar" 100313 0x0 (set a1 (var sar))
+d "wsr a1, br" 100413 0x0 (set a1 (var br))
+d "wsr a1, litbase" 100513 0x0 (set a1 (var litbase))
+d "wsr a1, scompare1" 100c13 0x0 (set a1 (var scompare1))
+d "witlb a1, a2" 106250 0x0 nop