ssi*

rizinorg · Nov 27, 2024 · a3bf571 · a3bf571
1 parent 1c180d6
commit a3bf571
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diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -1214,6 +1214,19 @@ static RzAnalysisLiftedILOp op_ssai(XtensaContext *ctx) {
 	return SETG("sar", U32(IMM(0)));
 }
 
+static RzAnalysisLiftedILOp op_ssi(XtensaContext *ctx) {
+	return SEQ2(
+		SETL("vAddr", IMEM(1)),
+		STOREW(VARL("vAddr"), UNSIGNED(32, IREG(0))));
+}
+
+static RzAnalysisLiftedILOp op_ssip(XtensaContext *ctx) {
+	return SEQ3(
+		SETL("vAddr", IREG(1)),
+		STOREW(VARL("vAddr"), IREG(0)),
+		SETG(REGN(1), U32(IMM(2))));
+}
+
 #include <rz_il/rz_il_opbuilder_end.h>
 
 static const fn_analyze_op_il fn_tbl[] = {
@@ -1482,6 +1495,8 @@ static const fn_analyze_op_il fn_tbl[] = {
 	[XTENSA_INS_SRLI] = op_srli,
 	[XTENSA_INS_SSA8L] = op_ssa8l,
 	[XTENSA_INS_SSAI] = op_ssai,
+	[XTENSA_INS_SSI] = op_ssi,
+	[XTENSA_INS_SSIP] = op_ssip,
 };
 
 void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -264,3 +264,5 @@ d "srl a2, a1" 102091 0x0 (seq (set sa (& (>> (var sar) (bv 32 0x0) false) (>> (
 d "srli a2, a1, 1" 102141 0x0 (seq (set sa (bv 32 0x1)) (set a2 (>> (var a1) (var sa) false)))
 d "ssai 1" 004140 0x0 (set sar (bv 32 0x1))
 d "ssa8l a1" 002140 0x0 (set sar (<< (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false)) (bv 32 0x3) false))
+d "ssip f1, a2, 0x3fc" 13c2ff 0x0 (seq (set vAddr (var a2)) (storew 0 (var vAddr) (var f1)) (set a2 (bv 32 0x3fc)))
+d "ssi f1, a2, 0x3fc" 1342ff 0x0 (seq (set vAddr (+ (var a2) (bv 32 0x3fc))) (storew 0 (var vAddr) (cast 32 false (var f1))))