PIC: fixes

librz/analysis/arch/pic/pic18_analysis.inc → librz/arch/isa/pic/pic18_analysis.inc

@@ -3,8 +3,9 @@
 // SPDX-FileCopyrightText: 2015-2018 courk <[email protected]>
 // SPDX-License-Identifier: LGPL-3.0-only
 
-#include "../asm/arch/pic/pic_pic18.h"
+#include "pic_pic18.h"
 #include "pic18_esil.inc"
+#include "pic18_il.inc"
 
 static void pic18_cond_branch(RzAnalysisOp *aop, ut64 addr, const ut8 *buf) {
 	aop->type = RZ_ANALYSIS_OP_TYPE_CJMP;
@@ -19,7 +20,7 @@ static int analysis_pic_pic18_op(
 
 	aop->size = 2;
 	Pic18Op op = { 0 };
-	if (!pic18_disasm_op(&op, buf, len)) {
+	if (!pic18_disasm_op(&op, addr, buf, len)) {
 		goto err;
 	}
 	aop->size = op.size;
@@ -219,6 +220,10 @@ static int analysis_pic_pic18_op(
 		pic18_esil(aop, &op, addr, buf);
 	}
 
+	if (mask & RZ_ANALYSIS_OP_MASK_IL) {
+		aop->il_op = pic18_il(&op);
+	}
+
 	return aop->size;
 err:
 	aop->type = RZ_ANALYSIS_OP_TYPE_ILL;

librz/arch/isa/pic/pic18_il.inc

@@ -0,0 +1,5 @@
+#include <rz_il.h>
+
+static RzILOpEffect *pic18_il(Pic18Op *op) {
+	return NULL;
+}

librz/arch/isa/pic/pic_baseline.c

@@ -197,7 +197,7 @@ const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode) {
 	return &pic_baseline_op_info[opcode];
 }
 
-int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l) {
+int pic_baseline_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) {
 #define EMIT_INVALID \
 	{ \
 		op->size = 1; \

librz/arch/isa/pic/pic_baseline.h

@@ -78,6 +78,6 @@ typedef enum {
 PicBaselineOpcode pic_baseline_get_opcode(ut16 instr);
 PicBaselineOpArgs pic_baseline_get_opargs(PicBaselineOpcode opcode);
 const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode);
-int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l);
+int pic_baseline_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l);
 
 #endif // PIC_BASELINE_H

librz/analysis/arch/pic/pic_il.h → librz/arch/isa/pic/pic_il.h

@@ -70,6 +70,6 @@ RZ_IPI RzAnalysisILConfig *rz_midrange_il_vm_config(RZ_NONNULL RzAnalysis *analy
 
 // TODO: Add support for PIC18F & other device families
 
-#include "pic_midrange_il.c"
+#include "pic_midrange_il.inc"
 
 #endif // PIC_IL_H_

librz/arch/isa/pic/pic_midrange.c

@@ -180,7 +180,7 @@ const PicMidrangeOpAsmInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode) {
  *
  * \return Number of decoded bytes (2 on success, 1 on failure).
  * */
-int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l) {
+int pic_midrange_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) {
 	char fsr_op[6];
 	st16 branch;
 

librz/arch/isa/pic/pic_midrange.h

@@ -118,6 +118,6 @@ typedef enum {
 PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr);
 PicMidrangeOpArgs pic_midrange_get_opargs(PicMidrangeOpcode opcode);
 const PicMidrangeOpAsmInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode);
-int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l);
+int pic_midrange_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l);
 
 #endif // PIC_MIDRANGE_H

librz/analysis/arch/pic/pic_midrange_analysis.inc → librz/arch/isa/pic/pic_midrange_analysis.inc

@@ -4,7 +4,7 @@
 // SPDX-License-Identifier: LGPL-3.0-only
 
 #include "pic_il.h"
-#include "../../asm/arch/pic/pic_midrange.h"
+#include "pic_midrange.h"
 
 typedef void (*pic_midrange_inst_handler_t)(RzAnalysis *analysis, RzAnalysisOp *op,
 	ut64 addr,

librz/analysis/arch/pic/pic_midrange_il.c → librz/arch/isa/pic/pic_midrange_il.inc

@@ -6,7 +6,7 @@
 #include <stdlib.h>
 
 #include "pic_il.h"
-#include "../../asm/arch/pic/pic_midrange.h"
+#include "pic_midrange.h"
 
 #include <rz_il/rz_il_opbuilder_begin.h>
 

librz/arch/isa/pic/pic_pic18.c

@@ -101,14 +101,15 @@ static const Pic18OpDesc ops[] = {
 	{ PIC18_OPCODE_INVALID, 0x0, 0xffff, "invalid", NO_ARG },
 };
 
-bool pic18_disasm_op(Pic18Op *op, const ut8 *buff, ut64 len) {
+bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len) {
 #define check_len(x) \
 	if (len < x) { \
 		op->code = PIC18_OPCODE_INVALID; \
 		return false; \
 	} \
 	op->size = x;
 
+	op->addr = addr;
 	check_len(2);
 	ut16 word = rz_read_le16(buff);
 	Pic18OpDesc *desc = (Pic18OpDesc *)ops;
@@ -185,15 +186,15 @@ bool pic18_disasm_op(Pic18Op *op, const ut8 *buff, ut64 len) {
 	return true;
 }
 
-int pic_pic18_disassemble(RzAsmOp *asm_op, const ut8 *b, int blen) {
+int pic_pic18_disassemble(RzAsm *a, RzAsmOp *asm_op, const ut8 *b, int blen) {
 	asm_op->size = 2;
 	Pic18Op op = { 0 };
-	pic18_disasm_op(&op, b, blen);
-
-	if (op.code == PIC18_OPCODE_INVALID) {
+	if (!pic18_disasm_op(&op, a->pc, b, blen) ||
+		op.code == PIC18_OPCODE_INVALID) {
 		rz_asm_op_set_asm(asm_op, op.mnemonic);
 		return -1;
 	}
+	asm_op->size = op.size;
 	switch (op.args_kind) {
 	case NO_ARG:
 		rz_asm_op_set_asm(asm_op, op.mnemonic);

librz/arch/isa/pic/pic_pic18.h

@@ -103,6 +103,7 @@ typedef enum {
 } Pic18ArgsKind;
 
 typedef struct {
+	ut64 addr;
 	Pic18Opcode code;
 	const char *mnemonic;
 	ut8 size;
@@ -118,7 +119,7 @@ typedef struct {
 	};
 } Pic18Op;
 
-bool pic18_disasm_op(Pic18Op *op, const ut8 *buff, ut64 len);
-int pic_pic18_disassemble(RzAsmOp *asm_op, const ut8 *b, int l);
+bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len);
+int pic_pic18_disassemble(RzAsm *a, RzAsmOp *asm_op, const ut8 *b, int l);
 
 #endif // PIC_PIC18_H