isync

rizinorg · Nov 21, 2024 · c3e8782 · c3e8782
1 parent 259840d
commit c3e8782
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diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -480,11 +480,16 @@ static RzAnalysisLiftedILOp op_float_s(XtensaContext *ctx) {
 				INT2F(RZ_FLOAT_IEEE754_BIN_32, RZ_FLOAT_RMODE_RNA, DIV(IREG(1), U32(pow(2, -IMM(2))))))));
 }
 
+// FIXME: statusflags
 static RzAnalysisLiftedILOp op_floor_s(XtensaContext *ctx) {
 	return SETG(REGN(0),
 		F2SINT(32, RZ_FLOAT_RMODE_RNA, FMUL(RZ_FLOAT_RMODE_RNA, FLOATV32(IREG(1)), F32(pow(2, IMM(2))))));
 }
 
+static RzAnalysisLiftedILOp op_isync(XtensaContext *ctx) {
+	return NOP();
+}
+
 #include <rz_il/rz_il_opbuilder_end.h>
 
 static const fn_analyze_op_il fn_tbl[] = {
@@ -557,6 +562,7 @@ static const fn_analyze_op_il fn_tbl[] = {
 	[XTENSA_INS_EXTW] = op_extw,
 	[XTENSA_INS_FLOAT_S] = op_float_s,
 	[XTENSA_INS_FLOOR_S] = op_floor_s,
+	[XTENSA_INS_ISYNC] = op_isync,
 };
 
 void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -77,3 +77,4 @@ d "extui a2, a1, 0x13, 5" 102345 0x0 (set a2 (let at (var a1) (& (bv 32 0x3f) (l
 d "extw" d02000 0x0 nop
 d "float.s f2, a3, 1" 1023ca 0x0 (set f2 (cast 64 false (fbits (fcast_float ieee754-bin32 rna (div (var a3) (bv 32 0x0))))))
 d "floor.s a2, f3, 1" 1023aa 0x0 (set a2 (fcast_sint 32 rna (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) ))))
+d "" 002000 0 ()