Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix compilation for cs4 and cs5 #4913

Merged
merged 1 commit into from
Feb 18, 2025
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 14 additions & 1 deletion librz/arch/isa/mips/mips_il.c
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@

#include "mips_internal.h"

#if CS_NEXT_VERSION > 5
#include <rz_il/rz_il_opbuilder_begin.h>

#define VARG_REG(idx) VARG(REG(idx))
Expand Down Expand Up @@ -2751,5 +2752,17 @@ RZ_IPI RzAnalysisILConfig *mips_il_config(RzAnalysis *analysis) {
}
return r;
}

#include <rz_il/rz_il_opbuilder_end.h>

#else // CS_NEXT_VERSION < 6
// Capstone before v6 has a very broken MIPS support.
// we cannot support it for RzIL.

RZ_IPI RzILOpEffect *mips_il(RZ_NONNULL const csh *handle, RZ_NONNULL const cs_insn *insn, const ut32 gprlen) {
return NULL;
}

RZ_IPI RzAnalysisILConfig *mips_il_config(RzAnalysis *analysis) {
return NULL;
}
#endif // CS_NEXT_VERSION
12 changes: 6 additions & 6 deletions librz/arch/p/arch_mips_cs.c
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@
#else
// first cpu is default
#define CAPSTONE_CPUS "mips32,mips1,mips2,mips32r2,mips32r3,mips32r5,mips32r6,mips3,mips4,mips5,mips64r2,mips64r3,mips64r5,mips64r6,octeon,octeonp,nanomips,nms1,i7200,micromips,micro32r3,micro32r6"
#define CAPSTONE_FEATURES "noptr64,nofloat"
#define CAPSTONE_FEATURES "+noptr64,+nofloat,+gpr32,+gpr64"
#endif

#define MIPS_CPUS CAPSTONE_CPUS "," EXTRA_CPUS "," CAPSTONE_FEATURES
Expand All @@ -61,10 +61,6 @@

static bool cs_mode_from_cpu(const char *cpu, int bits, bool big_endian, cs_mode *mode, ut32 *gpr_size) {
cs_mode _mode = (big_endian) ? CS_MODE_BIG_ENDIAN : CS_MODE_LITTLE_ENDIAN;
ut32 _add_gpr_size = bits > 0 ? bits : 32;

bool force_gpr32 = has_special_cpu_flag(cpu, "+gpr32");
bool force_gpr64 = has_special_cpu_flag(cpu, "+gpr64");

#if CS_NEXT_VERSION < 6
switch (bits) {
Expand Down Expand Up @@ -120,6 +116,10 @@ static bool cs_mode_from_cpu(const char *cpu, int bits, bool big_endian, cs_mode
}

#else // CS_NEXT_VERSION >= 6
ut32 _add_gpr_size = bits > 0 ? bits : 32;
bool force_gpr32 = has_special_cpu_flag(cpu, "+gpr32");
bool force_gpr64 = has_special_cpu_flag(cpu, "+gpr64");

#define return_or_add_on_cpu(cpu_name, mode_flag, gprlen) \
do { \
if (!strcmp(cpu, cpu_name)) { \
Expand Down Expand Up @@ -225,7 +225,6 @@ static bool cs_mode_from_cpu(const char *cpu, int bits, bool big_endian, cs_mode
default:
return false;
}
#endif /* CS_NEXT_VERSION */

success:
if (gpr_size) {
Expand All @@ -237,6 +236,7 @@ static bool cs_mode_from_cpu(const char *cpu, int bits, bool big_endian, cs_mode
*gpr_size = _add_gpr_size;
}
}
#endif /* CS_NEXT_VERSION */
return true;
}
#undef return_on_cpu
Expand Down
6 changes: 4 additions & 2 deletions test/db/cmd/cmd_eval
Original file line number Diff line number Diff line change
Expand Up @@ -99,8 +99,10 @@ r10000
r12000
r14000
r16000
noptr64
nofloat
+noptr64
+nofloat
+gpr32
+gpr64
EOF
RUN

Expand Down
Loading