[LLVM][XTHeadVector] implement intrinsic vssra/vssrl (#124)

* [LLVM][XTHeadVector] define intrinsic `vssra/vssrl`

* [LLVM][XTHeadVector] define pseudos and patterns for `vssra/vssrl`

* [LLVM][XTHeadVector] add corresponding tests

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -706,6 +706,19 @@ let TargetPrefix = "riscv" in {
                     RISCVVIntrinsic {
     let VLOperand = 5;
   }
+  // For Saturating binary operations with mask but no policy.
+  // The destination vector type is the same as first source vector.
+  // The second source operand matches the destination type or is an XLen scalar.
+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vxrm, vl)
+  class XVSaturatingBinaryAAShiftMaskedRoundingMode
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
+                     LLVMMatchType<2>],
+                    [ImmArg<ArgIndex<4>>, IntrNoMem, IntrHasSideEffects]>,
+                    RISCVVIntrinsic {
+    let VLOperand = 6;
+  }
 
   // UnMasked Vector Multiply-Add operations, its first operand can not be undef.
   // Input: (vector_in, vector_in/scalar, vector_in, frm, vl)
@@ -890,6 +903,10 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME : RISCVSaturatingBinaryABShiftUnMaskedRoundingMode;
     def "int_riscv_" # NAME # "_mask" : XVSaturatingBinaryABShiftMaskedRoundingMode;
   }
+  multiclass XVSaturatingBinaryAAShiftRoundingMode {
+    def "int_riscv_" # NAME : RISCVSaturatingBinaryAAShiftUnMaskedRoundingMode;
+    def "int_riscv_" # NAME # "_mask" : XVSaturatingBinaryAAShiftMaskedRoundingMode;
+  }
 
   multiclass XVTernaryAAXARoundingMode {
     def "int_riscv_" # NAME : XVTernaryAAXAUnMaskedRoundingMode;
@@ -1057,6 +1074,10 @@ let TargetPrefix = "riscv" in {
   // 13.3.  Vector Single-Width Fractional Multiply with Rounding and Saturation Instructions
   defm th_vsmul : XVBinaryAAXRoundingMode;
 
+  // 13.5. Vector Single-Width Scaling Shift Instructions
+  defm th_vssrl : XVSaturatingBinaryAAShiftRoundingMode;
+  defm th_vssra : XVSaturatingBinaryAAShiftRoundingMode;
+
   // 13.6. Vector Narrowing Fixed-Point Clip Instructions
   defm th_vnclipu : XVSaturatingBinaryABShiftRoundingMode;
   defm th_vnclip : XVSaturatingBinaryABShiftRoundingMode;

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -2111,6 +2111,10 @@ multiclass XVPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constr
   defm _VI : XVPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 
+multiclass XVPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
+  defm _VI : XVPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;
+}
+
 multiclass XVPseudoBinaryV_VF<LMULInfo m, FPR_InfoXTHeadV f, string Constraint = "", int sew = 0> {
   defm "_V" # f.FX : XVPseudoBinary<m.vrclass, m.vrclass,
                                     f.fprclass, m, Constraint, sew>;
@@ -2431,6 +2435,24 @@ multiclass XVPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
   }
 }
 
+multiclass XVPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint = ""> {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVSShiftV_MX = !cast<SchedWrite>("WriteVSShiftV_" # mx);
+    defvar WriteVSShiftX_MX = !cast<SchedWrite>("WriteVSShiftX_" # mx);
+    defvar WriteVSShiftI_MX = !cast<SchedWrite>("WriteVSShiftI_" # mx);
+    defvar ReadVSShiftV_MX = !cast<SchedRead>("ReadVSShiftV_" # mx);
+    defvar ReadVSShiftX_MX = !cast<SchedRead>("ReadVSShiftX_" # mx);
+
+    defm "" : XVPseudoBinaryV_VV_RM<m, Constraint>,
+              Sched<[WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_VX_RM<m, Constraint>,
+              Sched<[WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_VI_RM<ImmType, m, Constraint>,
+              Sched<[WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask]>;
+  }
+}
+
 multiclass XVPseudoVNSHT_VV_VX_VI {
   foreach m = MxListWXTHeadV in {
     defvar mx = m.MX;
@@ -3731,6 +3753,18 @@ multiclass XVPatBinaryV_VI<string intrinsic, string instruction,
                       vti.RegClass, imm_type>;
 }
 
+multiclass XVPatBinaryV_VI_RM<string intrinsic, string instruction,
+                              list<VTypeInfo> vtilist,
+                              Operand imm_type> {
+  foreach vti = vtilist in
+    let Predicates = GetXVTypePredicates<vti>.Predicates in
+    defm : XVPatBinaryRoundingMode<intrinsic,
+                                   instruction # "_VI_" # vti.LMul.MX,
+                                   vti.Vector, vti.Vector, XLenVT, vti.Mask,
+                                   vti.Log2SEW, vti.RegClass,
+                                   vti.RegClass, imm_type>;
+}
+
 multiclass XVPatBinaryW_VV<string intrinsic, string instruction,
                            list<VTypeInfoToWide> vtilist> {
   foreach VtiToWti = vtilist in {
@@ -4612,6 +4646,12 @@ multiclass XVPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
       XVPatBinaryV_VX<intrinsic, instruction, vtilist>,
       XVPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
 
+multiclass XVPatBinaryV_VV_VX_VI_RM<string intrinsic, string instruction,
+                                    list<VTypeInfo> vtilist, Operand ImmType = simm5>
+    : XVPatBinaryV_VV_RM<intrinsic, instruction, vtilist>,
+      XVPatBinaryV_VX_RM<intrinsic, instruction, vtilist>,
+      XVPatBinaryV_VI_RM<intrinsic, instruction, vtilist, ImmType>;
+
 multiclass XVPatBinaryV_VV_VX<string intrinsic, string instruction,
                               list<VTypeInfo> vtilist, bit isSEWAware = 0>
     : XVPatBinaryV_VV<intrinsic, instruction, vtilist, isSEWAware>,
@@ -5422,14 +5462,28 @@ let Predicates = [HasVendorXTHeadV] in {
 // Saturation Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasVendorXTHeadV] in {
+let Predicates = [HasVendorXTHeadV], hasSideEffects = 1 in {
   defm PseudoTH_VSMUL  : XVPseudoVSMUL_VV_VX_RM;
 } // Predicates = [HasVendorXTHeadV]
 
 let Predicates = [HasVendorXTHeadV] in {
   defm : XVPatBinaryV_VV_VX_RM<"int_riscv_th_vsmul", "PseudoTH_VSMUL", AllIntegerXVectors>;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 13.5. Vector Single-Width Scaling Shift Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasVendorXTHeadV], hasSideEffects = 1 in {
+  defm PseudoTH_VSSRL : XVPseudoVSSHT_VV_VX_VI_RM<uimm5>;
+  defm PseudoTH_VSSRA : XVPseudoVSSHT_VV_VX_VI_RM<uimm5>;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_VV_VX_VI_RM<"int_riscv_th_vssrl", "PseudoTH_VSSRL", AllIntegerXVectors, uimm5>;
+  defm : XVPatBinaryV_VV_VX_VI_RM<"int_riscv_th_vssra", "PseudoTH_VSSRA", AllIntegerXVectors, uimm5>;
+} // Predicates = [HasVendorXTHeadV]
+
 //===----------------------------------------------------------------------===//
 // 13.6. Vector Narrowing Fixed-Point Clip Instructions
 //===----------------------------------------------------------------------===//