[LLVM][XTHeadVector] add option riscv-enable-vsetvli-elim

ruyisdk · Apr 15, 2024 · e2c070b · e2c070b
1 parent 4a52c3a
commit e2c070b
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -42,6 +42,11 @@ static cl::opt<bool> EnableRedundantCopyElimination(
     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
     cl::Hidden);
 
+static cl::opt<bool> EnableRedundantVSEVLIElimination(
+    "riscv-enable-vsetvli-elim",
+    cl::desc("Enable the redundant VSETVLI elimination pass"), cl::init(true),
+    cl::Hidden);
+
 // FIXME: Unify control over GlobalMerge.
 static cl::opt<cl::boolOrDefault>
     EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
@@ -401,6 +406,9 @@ void RISCVPassConfig::addOptimizedRegAlloc() {
 void RISCVPassConfig::addPostRegAlloc() {
   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination) {
     addPass(createRISCVRedundantCopyEliminationPass());
+  }
+  if (TM->getOptLevel() != CodeGenOpt::None &&
+      EnableRedundantVSEVLIElimination) {
     addPass(createRISCVRedundantVSETVLIEliminationPass());
   }
 }