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[LLVM][XTHeadVector] Fix RISCVInsertVSETVLI: handle hasAVLImm and constrain temporary register to be GPRNoX0 #121

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merged 2 commits into from
Jun 24, 2024

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@imkiva imkiva commented Jun 21, 2024

Depends on #120, tests will be updated after #120 is merged

@imkiva imkiva force-pushed the fix-imm-vsetvli-emulation branch from 6b14d8e to afd8d37 Compare June 24, 2024 02:24
@imkiva imkiva marked this pull request as ready for review June 24, 2024 02:24
@ChunyuLiao ChunyuLiao merged commit ce6e5b0 into ruyisdk:rebase-17.0.6 Jun 24, 2024
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imkiva added a commit to imkiva/llvm-project that referenced this pull request Feb 24, 2025
… constrain temporary register to be `GPRNoX0` (ruyisdk#121)

* [LLVM][XTHeadVector] Fix `Info.hasAVLImm()` branch

and constrain the temporary register to be `GPRNoX0`

* [LLVM][XTHeadVector] Update corresponding tests
imkiva added a commit to imkiva/llvm-project that referenced this pull request Feb 26, 2025
… constrain temporary register to be `GPRNoX0` (ruyisdk#121)

* [LLVM][XTHeadVector] Fix `Info.hasAVLImm()` branch

and constrain the temporary register to be `GPRNoX0`

* [LLVM][XTHeadVector] Update corresponding tests
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2 participants