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This repo includes all the SystemVerilog projects I have created in my digital design class, along with RTL and state machine diagrams, and simulation results. All simulations were done on Quartus Prime Lite.
sarpuser/SystemVerilog-Projects
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This repo includes all the SystemVerilog projects I have created in my digital design class, along with RTL and state machine diagrams, and simulation results. All simulations were done on Quartus Prime Lite.