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Promote bitfieldExtract and bitfieldInsert to become Slang intrinsics #5020

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7d44ee7
promoting bitfield extraction and insertion to become intrinsics for …
natevm Sep 6, 2024
554b4f0
removing duplicate intrinsics from glsl.meta.slang
natevm Sep 6, 2024
7eccd6c
reverting some unwanted changes
natevm Sep 6, 2024
1d6e26c
small formatting fixes
natevm Sep 6, 2024
783328f
adding test for bitfield extract, currently failing the sign extensio…
natevm Sep 6, 2024
00804a1
adding some tests for 32 bit and 64 bit bitfield insertion and extrac…
natevm Sep 9, 2024
648107f
adding more targets to test.
natevm Sep 9, 2024
a3529ca
fixing small regression when emitting component-wise bitfield ops for…
natevm Sep 10, 2024
d04bb68
updating spirv emit to account for non-32-bit ints
natevm Sep 10, 2024
4cd73c9
some refactoring for metal
natevm Sep 10, 2024
e189fd5
Merge branch 'master' into natevm-bitfield-instructions
natevm Sep 11, 2024
164a01b
making sign extension more robust to order ops which can vary between…
natevm Sep 13, 2024
fee1e81
Merge branch 'natevm-bitfield-instructions' of github.com:natevm/slan…
natevm Sep 13, 2024
fe183e2
updating slang emit metal to try to correct emitting 64-bit vector types
natevm Sep 15, 2024
8d2a47e
fixing missed switch cases
natevm Sep 15, 2024
7eb6b20
refactoring tests
natevm Sep 15, 2024
8561801
adding 16-bit test for bitfield insert
natevm Sep 15, 2024
9534072
Merge branch 'master' into natevm-bitfield-instructions
natevm Sep 15, 2024
fc0f6c8
fixing sign in insert test
natevm Sep 15, 2024
79d754a
Merge branch 'natevm-bitfield-instructions' of github.com:natevm/slan…
natevm Sep 15, 2024
b5e3ca5
Apply suggestions from code review
natevm Sep 15, 2024
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13 changes: 13 additions & 0 deletions source/slang/core.meta.slang
Original file line number Diff line number Diff line change
Expand Up @@ -2193,6 +2193,19 @@ __generic<T, U>
__intrinsic_op($(kIROp_Reinterpret))
T reinterpret(U value);

// Bitfield extract / insert
__generic<T>
[__readNone]
[__unsafeForceInlineEarly]
__intrinsic_op($(kIROp_BitfieldInsert))
T bitfieldInsert(T base, T insert, int offset, int bits);

__generic<T>
[__readNone]
[__unsafeForceInlineEarly]
__intrinsic_op($(kIROp_BitfieldExtract))
T bitfieldExtract(T value, int offset, int bits);

// Use an otherwise unused value
//
// This can be used to silence the warning about returning before initializing an out paramter.
Expand Down
162 changes: 0 additions & 162 deletions source/slang/glsl.meta.slang
Original file line number Diff line number Diff line change
Expand Up @@ -1150,168 +1150,6 @@ public void imulExtended(highp vector<int,N> x, highp vector<int,N> y, out highp
}
}

[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public int bitfieldExtract(int value, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldExtract";
case spirv: return spirv_asm {
result:$$int = OpBitFieldSExtract $value $offset $bits
};
default:
return int(uint(value >> offset) & ((1u << bits) - 1));
}
}

__generic<let N:int>
[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public vector<int,N> bitfieldExtract(vector<int,N> value, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldExtract";
case spirv: return spirv_asm {
result:$$vector<int,N> = OpBitFieldSExtract $value $offset $bits
};
default:
vector<int,N> result;
[ForceUnroll]
for (int i = 0; i < N; ++i)
{
result[i] = bitfieldExtract(value[i], offset, bits);
}
return result;
}
}

[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public uint bitfieldExtract(uint value, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldExtract";
case spirv: return spirv_asm {
result:$$uint = OpBitFieldUExtract $value $offset $bits
};
default:
return (value >> offset) & ((1u << bits) - 1);
}
}

__generic<let N:int>
[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public vector<uint,N> bitfieldExtract(vector<uint,N> value, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldExtract";
case spirv: return spirv_asm {
result:$$vector<uint,N> = OpBitFieldUExtract $value $offset $bits
};
default:
vector<uint,N> result;
[ForceUnroll]
for (int i = 0; i < N; ++i)
{
result[i] = bitfieldExtract(value[i], offset, bits);
}
return result;
}
}

[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public uint bitfieldInsert(uint base, uint insert, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldInsert";
case spirv: return spirv_asm {
result:$$uint = OpBitFieldInsert $base $insert $offset $bits
};
default:
uint clearMask = ~(((1u << bits) - 1u) << offset);
uint clearedBase = base & clearMask;
uint maskedInsert = (insert & ((1u << bits) - 1u)) << offset;
return clearedBase | maskedInsert;
}
}

__generic<let N:int>
[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public vector<uint,N> bitfieldInsert(vector<uint,N> base, vector<uint,N> insert, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldInsert";
case spirv: return spirv_asm {
result:$$vector<uint,N> = OpBitFieldInsert $base $insert $offset $bits
};
default:
vector<uint,N> result;
[ForceUnroll]
for (int i = 0; i < N; ++i)
{
result[i] = bitfieldInsert(base[i], insert[i], offset, bits);
}
return result;
}
}

[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public int bitfieldInsert(int base, int insert, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldInsert";
case spirv: return spirv_asm {
result:$$int = OpBitFieldInsert $base $insert $offset $bits
};
default:
uint clearMask = ~(((1u << bits) - 1u) << offset);
uint clearedBase = base & clearMask;
uint maskedInsert = (insert & ((1u << bits) - 1u)) << offset;
return clearedBase | maskedInsert;
}
}

__generic<let N:int>
[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
public vector<int,N> bitfieldInsert(vector<int,N> base, vector<int,N> insert, int offset, int bits)
{
__target_switch
{
case glsl: __intrinsic_asm "bitfieldInsert";
case spirv: return spirv_asm {
result:$$vector<int,N> = OpBitFieldInsert $base $insert $offset $bits
};
default:
vector<int,N> result;
[ForceUnroll]
for (int i = 0; i < N; ++i)
{
result[i] = bitfieldInsert(base[i], insert[i], offset, bits);
}
return result;
}
}

[__readNone]
[ForceInline]
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
Expand Down
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