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week5.md

shaoan edited this page Jan 7, 2022 · 1 revision

Bit

    IN in, load;
    OUT out;

    PARTS:
    // Put your code here:
    Mux(a=gayout, b=in, sel=load, out=a);
    DFF(in=a, out=out, out=gayout);}

bit

Register

    IN in[16], load;
    OUT out[16];

    PARTS:
    // Put your code here:
    Bit(in=in[0], load=load, out=out[0]);
    Bit(in=in[1], load=load, out=out[1]);
    Bit(in=in[2], load=load, out=out[2]);
    Bit(in=in[3], load=load, out=out[3]);
    Bit(in=in[4], load=load, out=out[4]);
    Bit(in=in[5], load=load, out=out[5]);
    Bit(in=in[6], load=load, out=out[6]);
    Bit(in=in[7], load=load, out=out[7]);
    Bit(in=in[8], load=load, out=out[8]);
    Bit(in=in[9], load=load, out=out[9]);
    Bit(in=in[10], load=load, out=out[10]);
    Bit(in=in[11], load=load, out=out[11]);
    Bit(in=in[12], load=load, out=out[12]);
    Bit(in=in[13], load=load, out=out[13]);
    Bit(in=in[14], load=load, out=out[14]);
    Bit(in=in[15], load=load, out=out[15]);}

Register

RAM8

    IN in[16], load, address[3];
    OUT out[16];

    PARTS:
    // Put your code here:
    DMux8Way(in=load, sel=address, a=a, b=b, c=c, d=d, e=e, f=f, g=g, h=h);
    Register(in=in, load=a, out=ra);
    Register(in=in, load=b, out=rb);
    Register(in=in, load=c, out=rc);
    Register(in=in, load=d, out=rd);
    Register(in=in, load=e, out=re);
    Register(in=in, load=f, out=rf);
    Register(in=in, load=g, out=rg);
    Register(in=in, load=h, out=rh);
    Mux8Way16(a=ra, b=rb, c=rc, d=rd, e=re, f=rf, g=rg, h=rh, sel=address, out=out);}

RAM8

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