Using high level synthesis to accelerate singular value decomposition (SVD), the most common matrix method.
Directory structure
README.md
code/
svd.h
svd.cpp
code_opt/
svd.h
svd.cpp
hls_library/
hls_svd.cpp
testdata/
svd_tb.cpp
pynq_python/
svd.py
script/
directives.tcl
run_hls.tcl
impl/
svd_top_csynth.rpt
- fpga board setup
We use Xilinx ZedBoard Evaluation and Development Kit to evaulate this project
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using HLS vivado to simulation and synthesis
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export RTL
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generate .bit from vivado
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python test
python svd.py
- xilinx vivado design examples
- fix negtive slack
- experiment on different scale floating number