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Update to latest SVD, rebuild using svd2rust 0.18.0 #11

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May 25, 2021
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Update to latest SVD, rebuild using svd2rust 0.18.0 #11

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57 changes: 28 additions & 29 deletions src/aon.rs
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Original file line number Diff line number Diff line change
@@ -1,65 +1,64 @@
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 2048usize],
#[doc = "0x800 - aon."]
#[doc = "0x00 - aon."]
pub aon: crate::Reg<aon::AON_SPEC>,
#[doc = "0x804 - aon_common."]
#[doc = "0x04 - aon_common."]
pub aon_common: crate::Reg<aon_common::AON_COMMON_SPEC>,
#[doc = "0x808 - aon_misc."]
#[doc = "0x08 - aon_misc."]
pub aon_misc: crate::Reg<aon_misc::AON_MISC_SPEC>,
_reserved3: [u8; 4usize],
#[doc = "0x810 - bg_sys_top."]
#[doc = "0x10 - bg_sys_top."]
pub bg_sys_top: crate::Reg<bg_sys_top::BG_SYS_TOP_SPEC>,
#[doc = "0x814 - dcdc18_top_0."]
#[doc = "0x14 - dcdc18_top_0."]
pub dcdc18_top_0: crate::Reg<dcdc18_top_0::DCDC18_TOP_0_SPEC>,
#[doc = "0x818 - dcdc18_top_1."]
#[doc = "0x18 - dcdc18_top_1."]
pub dcdc18_top_1: crate::Reg<dcdc18_top_1::DCDC18_TOP_1_SPEC>,
#[doc = "0x81c - ldo11soc_and_dctest."]
#[doc = "0x1c - ldo11soc_and_dctest."]
pub ldo11soc_and_dctest: crate::Reg<ldo11soc_and_dctest::LDO11SOC_AND_DCTEST_SPEC>,
#[doc = "0x820 - psw_irrcv."]
#[doc = "0x20 - psw_irrcv."]
pub psw_irrcv: crate::Reg<psw_irrcv::PSW_IRRCV_SPEC>,
_reserved8: [u8; 92usize],
#[doc = "0x880 - rf_top_aon."]
#[doc = "0x80 - rf_top_aon."]
pub rf_top_aon: crate::Reg<rf_top_aon::RF_TOP_AON_SPEC>,
#[doc = "0x884 - xtal_cfg."]
#[doc = "0x84 - xtal_cfg."]
pub xtal_cfg: crate::Reg<xtal_cfg::XTAL_CFG_SPEC>,
#[doc = "0x888 - tsen."]
#[doc = "0x88 - tsen."]
pub tsen: crate::Reg<tsen::TSEN_SPEC>,
_reserved11: [u8; 116usize],
#[doc = "0x900 - acomp0_ctrl."]
#[doc = "0x100 - acomp0_ctrl."]
pub acomp0_ctrl: crate::Reg<acomp0_ctrl::ACOMP0_CTRL_SPEC>,
#[doc = "0x904 - acomp1_ctrl."]
#[doc = "0x104 - acomp1_ctrl."]
pub acomp1_ctrl: crate::Reg<acomp1_ctrl::ACOMP1_CTRL_SPEC>,
#[doc = "0x908 - acomp_ctrl."]
#[doc = "0x108 - acomp_ctrl."]
pub acomp_ctrl: crate::Reg<acomp_ctrl::ACOMP_CTRL_SPEC>,
#[doc = "0x90c - gpadc_reg_cmd."]
#[doc = "0x10c - gpadc_reg_cmd."]
pub gpadc_reg_cmd: crate::Reg<gpadc_reg_cmd::GPADC_REG_CMD_SPEC>,
#[doc = "0x910 - gpadc_reg_config1."]
#[doc = "0x110 - gpadc_reg_config1."]
pub gpadc_reg_config1: crate::Reg<gpadc_reg_config1::GPADC_REG_CONFIG1_SPEC>,
#[doc = "0x914 - gpadc_reg_config2."]
#[doc = "0x114 - gpadc_reg_config2."]
pub gpadc_reg_config2: crate::Reg<gpadc_reg_config2::GPADC_REG_CONFIG2_SPEC>,
#[doc = "0x918 - adc converation sequence 1"]
#[doc = "0x118 - adc converation sequence 1"]
pub gpadc_reg_scn_pos1: crate::Reg<gpadc_reg_scn_pos1::GPADC_REG_SCN_POS1_SPEC>,
#[doc = "0x91c - adc converation sequence 2"]
#[doc = "0x11c - adc converation sequence 2"]
pub gpadc_reg_scn_pos2: crate::Reg<gpadc_reg_scn_pos2::GPADC_REG_SCN_POS2_SPEC>,
#[doc = "0x920 - adc converation sequence 3"]
#[doc = "0x120 - adc converation sequence 3"]
pub gpadc_reg_scn_neg1: crate::Reg<gpadc_reg_scn_neg1::GPADC_REG_SCN_NEG1_SPEC>,
#[doc = "0x924 - adc converation sequence 4"]
#[doc = "0x124 - adc converation sequence 4"]
pub gpadc_reg_scn_neg2: crate::Reg<gpadc_reg_scn_neg2::GPADC_REG_SCN_NEG2_SPEC>,
#[doc = "0x928 - gpadc_reg_status."]
#[doc = "0x128 - gpadc_reg_status."]
pub gpadc_reg_status: crate::Reg<gpadc_reg_status::GPADC_REG_STATUS_SPEC>,
#[doc = "0x92c - gpadc_reg_isr."]
#[doc = "0x12c - gpadc_reg_isr."]
pub gpadc_reg_isr: crate::Reg<gpadc_reg_isr::GPADC_REG_ISR_SPEC>,
#[doc = "0x930 - gpadc_reg_result."]
#[doc = "0x130 - gpadc_reg_result."]
pub gpadc_reg_result: crate::Reg<gpadc_reg_result::GPADC_REG_RESULT_SPEC>,
#[doc = "0x934 - gpadc_reg_raw_result."]
#[doc = "0x134 - gpadc_reg_raw_result."]
pub gpadc_reg_raw_result: crate::Reg<gpadc_reg_raw_result::GPADC_REG_RAW_RESULT_SPEC>,
#[doc = "0x938 - gpadc_reg_define."]
#[doc = "0x138 - gpadc_reg_define."]
pub gpadc_reg_define: crate::Reg<gpadc_reg_define::GPADC_REG_DEFINE_SPEC>,
#[doc = "0x93c - hbncore_resv0."]
#[doc = "0x13c - hbncore_resv0."]
pub hbncore_resv0: crate::Reg<hbncore_resv0::HBNCORE_RESV0_SPEC>,
#[doc = "0x940 - hbncore_resv1."]
#[doc = "0x140 - hbncore_resv1."]
pub hbncore_resv1: crate::Reg<hbncore_resv1::HBNCORE_RESV1_SPEC>,
}
#[doc = "aon register accessor: an alias for `Reg<AON_SPEC>`"]
Expand Down
16 changes: 8 additions & 8 deletions src/aon/acomp0_ctrl.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ impl<'a> ACOMP0_MUXEN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26);
self.w
}
}
Expand All @@ -90,7 +90,7 @@ impl<'a> ACOMP0_POS_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x0f << 22)) | (((value as u32) & 0x0f) << 22);
self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22);
self.w
}
}
Expand All @@ -116,7 +116,7 @@ impl<'a> ACOMP0_NEG_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u32) & 0x0f) << 18);
self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18);
self.w
}
}
Expand All @@ -142,7 +142,7 @@ impl<'a> ACOMP0_LEVEL_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x3f << 12)) | (((value as u32) & 0x3f) << 12);
self.w.bits = (self.w.bits & !(0x3f << 12)) | ((value as u32 & 0x3f) << 12);
self.w
}
}
Expand All @@ -168,7 +168,7 @@ impl<'a> ACOMP0_BIAS_PROG_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10);
self.w
}
}
Expand All @@ -194,7 +194,7 @@ impl<'a> ACOMP0_HYST_SELP_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 7)) | (((value as u32) & 0x07) << 7);
self.w.bits = (self.w.bits & !(0x07 << 7)) | ((value as u32 & 0x07) << 7);
self.w
}
}
Expand All @@ -220,7 +220,7 @@ impl<'a> ACOMP0_HYST_SELN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
self.w
}
}
Expand Down Expand Up @@ -256,7 +256,7 @@ impl<'a> ACOMP0_EN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
Expand Down
16 changes: 8 additions & 8 deletions src/aon/acomp1_ctrl.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ impl<'a> ACOMP1_MUXEN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26);
self.w
}
}
Expand All @@ -90,7 +90,7 @@ impl<'a> ACOMP1_POS_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x0f << 22)) | (((value as u32) & 0x0f) << 22);
self.w.bits = (self.w.bits & !(0x0f << 22)) | ((value as u32 & 0x0f) << 22);
self.w
}
}
Expand All @@ -116,7 +116,7 @@ impl<'a> ACOMP1_NEG_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u32) & 0x0f) << 18);
self.w.bits = (self.w.bits & !(0x0f << 18)) | ((value as u32 & 0x0f) << 18);
self.w
}
}
Expand All @@ -142,7 +142,7 @@ impl<'a> ACOMP1_LEVEL_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x3f << 12)) | (((value as u32) & 0x3f) << 12);
self.w.bits = (self.w.bits & !(0x3f << 12)) | ((value as u32 & 0x3f) << 12);
self.w
}
}
Expand All @@ -168,7 +168,7 @@ impl<'a> ACOMP1_BIAS_PROG_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10);
self.w
}
}
Expand All @@ -194,7 +194,7 @@ impl<'a> ACOMP1_HYST_SELP_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 7)) | (((value as u32) & 0x07) << 7);
self.w.bits = (self.w.bits & !(0x07 << 7)) | ((value as u32 & 0x07) << 7);
self.w
}
}
Expand All @@ -220,7 +220,7 @@ impl<'a> ACOMP1_HYST_SELN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
self.w
}
}
Expand Down Expand Up @@ -256,7 +256,7 @@ impl<'a> ACOMP1_EN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
Expand Down
72 changes: 9 additions & 63 deletions src/aon/acomp_ctrl.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ impl<'a> ACOMP_RESERVED_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24);
self.w
}
}
Expand All @@ -72,28 +72,6 @@ impl core::ops::Deref for ACOMP0_OUT_RAW_R {
&self.0
}
}
#[doc = "Field `acomp0_out_raw` writer - "]
pub struct ACOMP0_OUT_RAW_W<'a> {
w: &'a mut W,
}
impl<'a> ACOMP0_OUT_RAW_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
self.w
}
}
#[doc = "Field `acomp1_out_raw` reader - "]
pub struct ACOMP1_OUT_RAW_R(crate::FieldReader<bool, bool>);
impl ACOMP1_OUT_RAW_R {
Expand All @@ -108,28 +86,6 @@ impl core::ops::Deref for ACOMP1_OUT_RAW_R {
&self.0
}
}
#[doc = "Field `acomp1_out_raw` writer - "]
pub struct ACOMP1_OUT_RAW_W<'a> {
w: &'a mut W,
}
impl<'a> ACOMP1_OUT_RAW_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
self.w
}
}
#[doc = "Field `acomp0_test_sel` reader - "]
pub struct ACOMP0_TEST_SEL_R(crate::FieldReader<u8, u8>);
impl ACOMP0_TEST_SEL_R {
Expand All @@ -152,7 +108,7 @@ impl<'a> ACOMP0_TEST_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12);
self.w
}
}
Expand All @@ -178,7 +134,7 @@ impl<'a> ACOMP1_TEST_SEL_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10);
self.w
}
}
Expand Down Expand Up @@ -214,7 +170,7 @@ impl<'a> ACOMP0_TEST_EN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
self.w
}
}
Expand Down Expand Up @@ -250,7 +206,7 @@ impl<'a> ACOMP1_TEST_EN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
self.w
}
}
Expand Down Expand Up @@ -286,7 +242,7 @@ impl<'a> ACOMP0_RSTN_ANA_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
Expand Down Expand Up @@ -322,7 +278,7 @@ impl<'a> ACOMP1_RSTN_ANA_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
Expand Down Expand Up @@ -379,16 +335,6 @@ impl W {
pub fn acomp_reserved(&mut self) -> ACOMP_RESERVED_W {
ACOMP_RESERVED_W { w: self }
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn acomp0_out_raw(&mut self) -> ACOMP0_OUT_RAW_W {
ACOMP0_OUT_RAW_W { w: self }
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn acomp1_out_raw(&mut self) -> ACOMP1_OUT_RAW_W {
ACOMP1_OUT_RAW_W { w: self }
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn acomp0_test_sel(&mut self) -> ACOMP0_TEST_SEL_W {
Expand Down Expand Up @@ -438,10 +384,10 @@ impl crate::Readable for ACOMP_CTRL_SPEC {
impl crate::Writable for ACOMP_CTRL_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets acomp_ctrl to value 0"]
#[doc = "`reset()` method sets acomp_ctrl to value 0x03"]
impl crate::Resettable for ACOMP_CTRL_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
0x03
}
}
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