OpenPiton Transducer in WARP-V

formal/warp-v_formal.tlv

@@ -3,12 +3,67 @@ m4+definitions
    m4_define(['M4_ISA'], ['RISCV'])
    // Configure for formal verification.
    m4_define(['M4_FORMAL'], 1)
+   m4_define(['M4_OPENPITON'], 0)
    m4_define(['M4_RISCV_FORMAL_ALTOPS'], 1)
    m4_define(['M4_VIZ'], 0)
    m4_define(['M4_STANDARD_CONFIG'], ['1-stage'])
+
 \SV
    // Include WARP-V.
    m4_include_lib(['./warp-v.tlv'])
+   module dmem_ext #(parameter SIZE = 1024, ADDR_WIDTH = 10, COL_WIDTH = 8, NB_COL	= 4) (
+      input    clk,
+      input    mem_valid,
+      input    mem_instr,
+      //output   mem_ready,
+      input    mem_ready,
+      input    [NB_COL*COL_WIDTH-1:0]  mem_addr,
+      input    [NB_COL*COL_WIDTH-1:0]  mem_wdata,
+      input    [NB_COL-1:0]            mem_wstrb,
+      output   [NB_COL*COL_WIDTH-1:0]  mem_rdata
+   );
+      //
+      //assign mem_ready = 1'b1;
+      reg [31:0] counter;
+      always @(posedge clk) begin
+         //if(reset)
+   //               counter <= 0;
+   //            else
+            counter <= counter + 1'b1;
+      end
+      /* verilator lint_off WIDTH */
+      //assign mem_ready = (counter % 2 == 0);
+      /* verilator lint_on WIDTH */
+      reg [NB_COL*COL_WIDTH-1:0] outputreg;   
+      reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
+      //
+      always @(posedge clk) begin
+         if(mem_ready) begin      //checking wstrb might be optional here
+            outputreg <= RAM[mem_addr];
+         end
+      end
+      //
+      assign mem_rdata = outputreg;
+      //
+      wire valid_write_locn;
+      assign valid_write_locn =  (mem_wstrb == 4'b1111) ||
+                                 (mem_wstrb == 4'b1100) ||
+                                 (mem_wstrb == 4'b0011) ||
+                                 (mem_wstrb == 4'b1000) ||
+                                 (mem_wstrb == 4'b0100) ||
+                                 (mem_wstrb == 4'b0010) ||
+                                 (mem_wstrb == 4'b0001) ;
+      //
+      generate
+            genvar i;
+            for (i = 0; i < NB_COL; i = i+1) begin
+            always @(posedge clk) begin 
+               if (mem_valid && mem_wstrb[i] && valid_write_locn) 
+                  RAM[mem_addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= mem_wdata[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
+               end
+            end
+      endgenerate        
+   endmodule
 m4+module_def
 \TLV
    m4+warpv()

impl/Makefile

@@ -20,7 +20,7 @@ out/%/status: warp-v_%.tlv ../warp-v.tlv
 		&& mv out/* . && rmdir out \
 		&& (exit `cat status`) \
 	  && sed -i 's/wire\( \[[^\[]\+\] L1_Mem_Value_\)/reg\1/' $(patsubst warp-v_%.tlv,warp-v_%.sv,$<) \
-	  && sed -i 's/wire\( \[[^\[]\+\] FETCH_Instr_Regs_vae_\)/reg\1/' $(patsubst %.tlv,%_gen.sv,$<)
+	  && sed -i 's/wire\( \[[^\[]\+\] FETCH_Instr_Regs_value_\)/reg\1/' $(patsubst %.tlv,%_gen.sv,$<)
 	@# Above sed HACKS fix bugs in the generated code.
 
 impl:

openpiton/byte_en.tlv

@@ -0,0 +1,95 @@
+\m4_TLV_version 1d: tl-x.org
+\SV
+// m4_define_vector(['M4_INSTR'], 32)					// ISA dependent instr width
+// m4_define_vector(['M4_ADDR'], 32)					// ISA dependent address width
+   m4_define_hier(['M4_DATA_MEM_WORDS'], 32)		// number of dmem locations	
+   m4_define(['M4_BITS_PER_ADDR'], 8)  				// 8 for byte addressing.
+   m4_define_vector(['M4_WORD'], 32)					// machine width (RV32/64)
+   m4_define(['M4_ADDRS_PER_WORD'], m4_eval(M4_WORD_CNT / M4_BITS_PER_ADDR))
+   m4_define(['M4_SUB_WORD_BITS'], m4_width(m4_eval(M4_ADDRS_PER_WORD - 1)))
+//	m4_define_hier(M4_DATA_MEM_ADDRS, m4_eval(M4_DATA_MEM_WORDS_HIGH * M4_ADDRS_PER_WORD))  // Addressable data memory locations, 
+                                                                                            //	can be useful in future
+
+	module dmem_ext #(parameter SIZE = 1024, ADDR_WIDTH = 10, COL_WIDTH = 8, NB_COL	= 4) (
+      input   clk,
+      input   [NB_COL-1:0]	        we,            // for enabling individual column accessible (for writes)
+      input   [ADDR_WIDTH-1:0]	    addr,      
+      input   [NB_COL*COL_WIDTH-1:0]  din,
+      output  [NB_COL*COL_WIDTH-1:0]  dout
+   );
+
+      reg [NB_COL*COL_WIDTH-1:0] outputreg;   
+      reg	[NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
+
+      always @(posedge clk) begin
+            outputreg <= RAM[addr];
+      end
+
+      assign dout = outputreg;
+
+      generate
+            genvar i;
+            for (i = 0; i < NB_COL; i = i+1) begin
+            always @(posedge clk) begin 
+               if (we[i]) 
+                  RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
+               end
+            end
+      endgenerate
+
+   endmodule 
+
+   m4_makerchip_module   // (Expanded in Nav-TLV pane.)
+
+\TLV fake_dmem_sv(/_top, /_scope, $_clk, $_addr, $_write, $_din, $_dout)
+   /_scope
+      \SV_plus
+         dmem_ext #(
+               .SIZE(M4_DATA_MEM_WORDS_HIGH), 
+               .ADDR_WIDTH(M4_DATA_MEM_WORDS_INDEX_HIGH), 
+               .COL_WIDTH(M4_WORD_HIGH / M4_ADDRS_PER_WORD), 
+               .NB_COL(M4_ADDRS_PER_WORD)
+               )
+         dmem_ext (
+               .clk     (/_top$_clk),
+               .addr    (/_top$_addr[M4_DATA_MEM_WORDS_INDEX_MAX + M4_SUB_WORD_BITS : M4_SUB_WORD_BITS]),
+               .we      (/_top$_write),
+               .din     (/_top$_din), 
+               .dout    (/_top$['']$_dout[31:0])
+               );
+
+\TLV
+   |mem
+      @0
+         $clk = *clk;
+         $addr[6:0]  =  (!(*reset) && *cyc_cnt < 3)  ? 6'h0  :
+                        (*cyc_cnt < 4)  ? 6'h1  :
+                        (*cyc_cnt < 5)  ? 6'h2  :
+                        (*cyc_cnt < 6)  ? 6'h3  :
+                        (*cyc_cnt < 7)  ? 6'h10 :
+                        (*cyc_cnt < 9)  ? 6'h0  :
+                        (*cyc_cnt < 10) ? 6'h4  :
+                        (*cyc_cnt < 11) ? 6'h8  :
+                        (*cyc_cnt < 12) ? 6'hc  : 
+                                          6'hXX ;
+
+         $write[3:0] =  (!(*reset) && *cyc_cnt <3) ?  4'b0001 :
+                        (*cyc_cnt <4) ?  4'b0010 :
+                        (*cyc_cnt <5) ?  4'b0100 : 
+                        (*cyc_cnt <6) ?  4'b1000 :  
+                        (*cyc_cnt <7) ?  4'b1111 :
+                                         4'b0;
+
+         $din[31:0]  =  (!(*reset) && *cyc_cnt < 3) ?  32'hCA :
+                        (*cyc_cnt < 4) ?  32'hBA << 8 :
+                        (*cyc_cnt < 5) ?  32'hDE << 16 :
+                        (*cyc_cnt < 6) ?  32'h55 << 24:
+                                          32'h1234 ;
+
+         m4+fake_dmem_sv(|mem, /memscope, $clk, $addr, $write, $din, $dout)
+         `BOGUS_USE($dout)
+   // Assert these to end simulation (before Makerchip cycle limit).
+   *passed = *cyc_cnt > 40;
+   *failed = 1'b0;
+\SV
+   endmodule

openpiton/dmem_ext.sv

@@ -0,0 +1,29 @@
+   module dmem_ext #(parameter SIZE = 1024, ADDR_WIDTH = 10, COL_WIDTH = 8, NB_COL	= 4) (
+      input   clk, valid_st, spec_ld,
+      input   [NB_COL-1:0]	        we,            // for enabling individual column accessible (for writes)
+      input   [ADDR_WIDTH-1:0]	    addr,      
+      input   [NB_COL*COL_WIDTH-1:0]  din,
+      output  [NB_COL*COL_WIDTH-1:0]  dout
+   );
+
+      reg [NB_COL*COL_WIDTH-1:0] outputreg;   
+      reg	[NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
+
+      always @(posedge clk) begin
+         if(spec_ld) begin
+            outputreg <= RAM[addr];
+         end
+      end
+
+      assign dout = outputreg;
+
+      generate
+            genvar i;
+            for (i = 0; i < NB_COL; i = i+1) begin
+            always @(posedge clk) begin 
+               if (valid_st && we[i]) 
+                  RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
+               end
+            end
+      endgenerate        
+   endmodule

openpiton/fake_dmem_sv.tlv

@@ -0,0 +1,85 @@
+\m4_TLV_version 1d: tl-x.org
+\SV
+   m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
+   m4_define_vector(['M4_INSTR'], 32)
+   m4_define_vector(['M4_ADDR'], 32)
+   m4_define(['M4_BITS_PER_ADDR'], 8)  // 8 for byte addressing.
+   m4_define_vector(['M4_WORD'], 32)
+   // Default Makerchip TL-Verilog Code Template
+   m4_define(['M4_ADDRS_PER_WORD'], m4_eval(M4_WORD_CNT / M4_BITS_PER_ADDR))
+   m4_define(['M4_SUB_WORD_BITS'], m4_width(m4_eval(M4_ADDRS_PER_WORD - 1)))
+
+	module twoport4(
+      input logic clk,
+      input logic rst,
+      input logic [6:0] ra, wa,
+      input logic write,
+      input logic [31:0] d,
+      output logic [31:0] q);
+
+      logic [31:0] mem [0:127];
+
+      integer i;
+
+      always_ff @(posedge clk) begin
+      if(rst) begin
+         for(i=0;i<128;i=i+1)
+           assign mem[i] = 0;
+      end
+      else begin
+         if (write) mem[wa] <= d;
+         q <= mem[ra];
+      end
+      end
+
+   endmodule 
+   // =========================================
+   // Welcome!  Try the tutorials via the menu.
+   // =========================================
+
+   // Macro providing required top-level module definition, random
+   // stimulus support, and Verilator config.
+   m4_makerchip_module   // (Expanded in Nav-TLV pane.)
+
+\TLV fake_dmem_sv(/_top, /_scope, $_clk, $_rst, $_ra, $_wa, $_write, $_d, $_q)
+   /_scope
+      \SV_plus
+         twoport4 twoport4(.clk     (/_top$_clk),
+                           .rst     (/_top$_rst),
+                           .ra      (/_top$_ra),
+                           .wa      (/_top$_wa),
+                           .write   (/_top$_write),
+                           .d       (/_top$_d), 
+                           .q       (/_top$['']$_q[31:0]));
+
+\TLV
+   |mem
+      @0
+         $reset = *reset;
+         $clk = *clk;
+         $ra[6:0] =  (*cyc_cnt < 3) ? 6'h0 :
+                     (*cyc_cnt < 4) ? 6'h1 :
+                     (*cyc_cnt < 5) ? 6'h2 :
+                     (*cyc_cnt < 6) ? 6'h3 :
+                                      6'h4 ;
+
+         $wa[6:0] =  (*cyc_cnt < 2) ? 6'h0 :
+                     (*cyc_cnt < 3) ? 6'h1 :
+                     (*cyc_cnt < 4) ? 6'h2 :
+                     (*cyc_cnt < 5) ? 6'h3 :
+                                      6'h10 ;
+         //$wa[6:0] = 6'b0;
+         $write = 1'b1;
+         $d[31:0] =  (*cyc_cnt < 2) ? 32'hCAFE :
+                     (*cyc_cnt < 3) ? 32'hBABE :
+                     (*cyc_cnt < 4) ? 32'hDEAD :
+                     (*cyc_cnt < 5) ? 32'h5555 :
+                                      32'h1234 ;
+      //|mem
+         m4+fake_dmem_sv(|mem, /memscope, $clk, $reset, $ra, $wa, $write, $d, $q)
+
+   // Assert these to end simulation (before Makerchip cycle limit).
+   *passed = *cyc_cnt > 40;
+   *failed = 1'b0;
+\SV
+   endmodule