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Report each line that has a var decl in an unnamed block
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,3 @@ | ||
./ivltests/br_gh1182.v:3: error: Variable declaration in unnamed block requires SystemVerilog. | ||
./ivltests/br_gh1182.v:4: error: Variable declaration in unnamed block requires SystemVerilog. | ||
./ivltests/br_gh1182.v:8: error: Variable declaration in unnamed block requires SystemVerilog. |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,11 @@ | ||
module top; | ||
initial begin | ||
logic [7:0] data; | ||
logic [3:0] tmp; | ||
end | ||
|
||
initial begin | ||
logic [3:0] nib; | ||
$display("PASSED"); | ||
end | ||
endmodule |
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