fix undefined behaviour

src/crc.rs

@@ -19,7 +19,6 @@
 use crate::rcc::{Enable, Rcc, Reset};
 use crate::stm32::CRC;
 use core::hash::Hasher;
-use core::ptr;
 
 /// Extension trait to constrain the CRC peripheral.
 pub trait CrcExt {
@@ -170,11 +169,8 @@ impl Crc {
     pub fn feed(&mut self, data: &[u8]) {
         let crc = unsafe { &(*CRC::ptr()) };
         for byte in data {
-            unsafe {
-                // Workaround with svd2rust, it does not generate the byte interface to the DR
-                // register
-                ptr::write_volatile(&crc.dr as *const _ as *mut u8, *byte);
-            }
+            let ptr = &crc.dr as *const _;
+            unsafe { core::ptr::write_volatile(ptr as *mut u8, *byte) };
         }
     }
 

src/spi.rs

@@ -262,8 +262,8 @@ macro_rules! spi {
                 } else if sr.crcerr().bit_is_set() {
                     nb::Error::Other(Error::Crc)
                 } else if sr.txe().bit_is_set() {
-                    // NOTE(write_volatile) see note above
-                    unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u8, byte) }
+                    let ptr = &self.spi.dr as *const _;
+                    unsafe { core::ptr::write_volatile(ptr as *mut u8, byte) };
                     return Ok(());
                 } else {
                     nb::Error::WouldBlock