[rtl] use past SDA in twd FSM transition (#1165)

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 22.01.2025 | 1.10.9.10 | :bug: fix TWD ACK/NACK sampling | [#1165](https://github.com/stnolting/neorv32/pull/1165) |
 | 18.01.2025 | 1.10.9.9 | atomic memory access updates and improvements | [#1163](https://github.com/stnolting/neorv32/pull/1163) |
 | 16.01.2025 | 1.10.9.8 | :bug: fix several TWD design flaws | [#1161](https://github.com/stnolting/neorv32/pull/1161) |
 | 15.01.2025 | 1.10.9.7 | :sparkles: add GPIO interrupt(s); :warning: remove XIRQ controller, constrain GPIO input/output ports from 64-bit to 32-bit | [#1159](https://github.com/stnolting/neorv32/pull/1159) |

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100909"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100910"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

rtl/core/neorv32_twd.vhd

@@ -107,6 +107,7 @@ architecture neorv32_twd_rtl of neorv32_twd is
     cmd   : std_ulogic; -- 0 = write, 1 = read
     rdata : std_ulogic_vector(7 downto 0); -- read-access data
     dout  : std_ulogic; -- output bit
+    ack   : std_ulogic; -- ACK/NACK after transmission
     busy  : std_ulogic; -- bus operation in progress
     wr_we : std_ulogic; -- write write-enable
     rd_re : std_ulogic; -- read read-enable
@@ -321,6 +322,7 @@ begin
       engine.sreg  <= (others => '1');
       engine.cmd   <= '0';
       engine.dout  <= '0';
+      engine.ack   <= '0';
       engine.wr_we <= '0';
       engine.rd_re <= '0';
     elsif rising_edge(clk_i) then
@@ -417,10 +419,14 @@ begin
           if (ctrl.enable = '0') or (smp.stop = '1') then -- disabled or stop-condition
             engine.state <= S_IDLE;
           elsif (smp.scl_fall = '1') then -- end of this time slot
-            if (engine.cmd = '0') or ((engine.cmd = '1') and (smp.sda = '0')) then -- WRITE or READ with ACK
+            if (engine.cmd = '0') or ((engine.cmd = '1') and (engine.ack = '0')) then -- WRITE or READ-with-ACK
               engine.state <= S_RTX;
             end if;
           end if;
+          -- sample bus on rising edge --
+          if (smp.scl_rise = '1') then
+            engine.ack <= smp.sda;
+          end if;
           -- [READ] advance to next data byte if ACK is send by host --
           if (engine.cmd = '1') and (smp.scl_rise = '1') and (smp.sda = '0') then
             engine.rd_re <= '1'; -- get next TX data byte