riscv: Add more comments

taiki-e · Nov 8, 2023 · c5751dc · c5751dc
1 parent 210b491
commit c5751dc
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/src/imp/riscv.rs b/src/imp/riscv.rs
@@ -2,6 +2,11 @@
 
 // Atomic load/store implementation on RISC-V.
 //
+// This is for RISC-V targets without atomic CAS. (rustc doesn't provide atomics
+// at all on such targets. https://github.com/rust-lang/rust/pull/114499)
+//
+// Also, optionally provides RMW implementation when force-amo is enabled.
+//
 // Refs:
 // - RISC-V Instruction Set Manual Volume I: Unprivileged ISA
 //   https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf