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^^ fixed library paths and testbench issues
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@talonmyburgh
talonmyburgh committed Dec 18, 2024
1 parent 76fbfd5 commit 8fe2766
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Showing 3 changed files with 102 additions and 43 deletions.
67 changes: 64 additions & 3 deletions casper_bus/run.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,67 @@
common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/fixed_pkg_c.vhd"))
common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/float_pkg_c.vhd"))
common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/common_pkg.vhd"))
common_pkg_lib.add_source_files(join(script_dir, "../common_pkg/tb_common_pkg.vhd"))

# TECHNOLOGY Library
technology_lib = vu.add_library("technology_lib")
technology_lib.add_source_files(join(script_dir, "../technology/technology_select_pkg.vhd"))

# XPM Library compile
lib_xpm = vu.add_library("xpm")
lib_xpm.add_source_files(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_VCOMP.vhd"))
xpm_source_file_base = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_base.vhd"))
xpm_source_file_sdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sdpram.vhd"))
xpm_source_file_tdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_tdpram.vhd"))
xpm_source_file_tdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sprom.vhd"))
xpm_source_file_tdpram = lib_xpm.add_source_file(join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_dprom.vhd"))
xpm_source_file_sdpram.add_dependency_on(xpm_source_file_base)
xpm_source_file_tdpram.add_dependency_on(xpm_source_file_base)

# Altera_mf library
lib_altera_mf = vu.add_library("altera_mf")
lib_altera_mf.add_source_file(join(script_dir, "../intel/altera_mf/altera_mf_components.vhd"))
altera_mf_source_file = lib_altera_mf.add_source_file(join(script_dir, "../intel/altera_mf/altera_mf.vhd"))

# STRATIXIV RAM Library
ip_stratixiv_ram_lib = vu.add_library("ip_stratixiv_ram_lib")
ip_stratix_file_cr_cw = ip_stratixiv_ram_lib.add_source_file(join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd"))
ip_stratix_file_crw_crw = ip_stratixiv_ram_lib.add_source_file(join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd"))
ip_stratix_file_cr_cw.add_dependency_on(altera_mf_source_file)
ip_stratix_file_crw_crw.add_dependency_on(altera_mf_source_file)

ip_xpm_ram_lib = vu.add_library("ip_xpm_ram_lib")
ip_xpm_file_cr_cw = ip_xpm_ram_lib.add_source_files(join(script_dir, "../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd"))
ip_xpm_file_cr_cw.add_dependency_on(xpm_source_file_sdpram)
ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(join(script_dir, "../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd"))
ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram)
ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(join(script_dir, "../ip_xpm/ram/ip_xpm_rom_r_r.vhd"))
ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram)

# Create library 'common_components_lib'
lib2 = vu.add_library("common_components_lib",allow_duplicate=True)
lib2.add_source_files(join(script_dir, "../common_components/*.vhd"))

# Create library 'ram_lib'
casper_ram_lib = vu.add_library("casper_ram_lib")
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_ram_pkg.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/tech_memory_component_pkg.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/tech_memory_ram_crw_crw.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/tech_memory_ram_cr_cw.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/tech_memory_rom_r.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/tech_memory_rom_r_r.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_ram_crw_crw.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_ram_rw_rw.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_rom_r_r.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_ram_r_w.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_paged_ram_r_w.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_paged_ram_rw_rw.vhd"))
casper_ram_lib.add_source_file(join(script_dir, "../casper_ram/common_paged_ram_crw_crw.vhd"))

# Create library 'casper_counter_lib'
casper_counter_lib = vu.add_library("casper_counter_lib")
casper_counter_lib.add_source_files(join(script_dir,"../casper_counter/common_counter.vhd"))
casper_counter_lib.add_source_files(join(script_dir,"../casper_counter/free_run_up_counter.vhd"))

# Create library 'common_slv_arr_pkg_lib'
common_slv_arr_pkg_lib = vu.add_library("common_slv_arr_pkg_lib")
Expand All @@ -34,22 +95,22 @@

# CASPER BUS Library
casper_bus_lib = vu.add_library("casper_bus_lib")
casper_bus_lib.add_source_file(join(script_dir, "./*.vhd"))
casper_bus_lib.add_source_files(join(script_dir, "*.vhd"))

TB_BUS_MUX = casper_bus_lib.test_bench("tb_tb_vu_bus_mux")
for delays in [0,1,2]:
for input_count in [2,3,6]:
for input_width in [4,8]:
TB_BUS_MUX.add_config(
name = f"Mux ({input_count} inputs of {input_width} bits)",
name = f"Mux (delay {delays} of {input_count} inputs of {input_width} bits)",
generics={
"g_delay": delays,
"g_nof_inputs": input_count,
"g_bit_width": input_width
}
)

TB_REPLICATE = casper_bus_lib.test_bench("tb_tb_vu_replicate")
TB_REPLICATE = casper_bus_lib.test_bench("tb_tb_vu_bus_replicate")
for delay in [0,1,2]:
for replication_factor in [2, 3]:
TB_REPLICATE.add_config(
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4 changes: 3 additions & 1 deletion casper_bus/tb_bus_mux.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,7 @@ begin
VARIABLE v_test_pass : BOOLEAN := TRUE;
VARIABLE v_count: UNSIGNED(g_bit_width-1 downto 0) := to_unsigned(0, g_bit_width);
VARIABLE v_value : STD_LOGIC_VECTOR(g_bit_width-1 downto 0);
VARIABLE s_exp_tmp : STD_LOGIC_VECTOR(g_bit_width-1 downto 0);
BEGIN
-- set inputs
-- index 0 will be time-variant, `v_count`
Expand Down Expand Up @@ -102,10 +103,11 @@ begin
END IF;

FOR r IN 0 to 2 LOOP
s_exp_tmp := STD_LOGIC_VECTOR(v_count);
slv_arr_set_variable(
s_idata,
0,
STD_LOGIC_VECTOR(v_count)
s_exp_tmp
);
-- s
WAIT FOR clk_period;
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74 changes: 35 additions & 39 deletions casper_bus/tb_bus_replicate.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -4,78 +4,74 @@

LIBRARY IEEE, common_pkg_lib;
USE IEEE.std_logic_1164.all;
USE ieee.numeric_std.all;
USE common_pkg_lib.common_pkg.ALL;

ENTITY tb_bus_replicate is
generic (
generic(
g_replication_factor : NATURAL := 2;
g_latency : NATURAL := 0;
g_replicated_value : NATURAL := 6
g_latency : NATURAL := 0;
g_replicated_value : NATURAL := 6
);
port (
o_clk : out std_logic;
o_tb_end : out std_logic;
o_test_msg : out STRING(1 to 80);
o_test_pass : out BOOLEAN
port(
o_clk : out std_logic;
o_tb_end : out std_logic;
o_test_msg : out STRING(1 to 80);
o_test_pass : out BOOLEAN
);
end ENTITY;

ARCHITECTURE rtl of tb_bus_replicate is
CONSTANT clk_period : TIME := 10 ns;
SIGNAL clk : std_logic := '1';
SIGNAL ce : std_logic := '1';
SIGNAL tb_end : STD_LOGIC := '0';
CONSTANT clk_period : TIME := 10 ns;

SIGNAL clk : std_logic := '1';
SIGNAL ce : std_logic := '1';
SIGNAL tb_end : STD_LOGIC := '0';

CONSTANT bit_width : NATURAL := ceil_log2(g_replicated_value);

SIGNAL s_in : std_logic_vector(bit_width-1 downto 0) := (others => '0');
SIGNAL s_out : std_logic_vector((bit_width*g_replication_factor)-1 downto 0) := (others => '0');
SIGNAL s_in : std_logic_vector(bit_width - 1 downto 0) := (others => '0');
SIGNAL s_out : std_logic_vector((bit_width * g_replication_factor) - 1 downto 0) := (others => '0');
begin

clk <= NOT clk OR tb_end AFTER clk_period / 2;
clk <= NOT clk OR tb_end AFTER clk_period / 2;

o_clk <= clk;
o_clk <= clk;
o_tb_end <= tb_end;

u_bus_replicate : entity work.bus_replicate
generic map (
generic map(
g_replication_factor => g_replication_factor,
g_latency => g_latency
g_latency => g_latency
)
port map (
clk => clk,
ce => ce,

port map(
clk => clk,
ce => ce,
i_data => s_in,
o_data => s_out
);

p_stim: process
variable v_din_index, v_dout_index: integer;
VARIABLE v_test_pass : BOOLEAN := TRUE;
VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.');
p_stim : process
variable v_din_index, v_dout_index : integer;
VARIABLE v_test_pass : BOOLEAN := TRUE;
VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.');
begin
ce <= '0';
ce <= '0';
s_in <= std_logic_vector(to_unsigned(g_replicated_value, bit_width));

wait until rising_edge(clk);
wait for 3*clk_period;
wait for 3 * clk_period;
ce <= '1';
wait for g_latency*clk_period;
wait for g_latency * clk_period;

for r in 0 to g_replication_factor loop
if g_replicated_value /= unsigned(s_out(
((r+1)*bit_width)-1 downto (r*bit_width)
)) then
v_test_msg := pad("Replication #"& integer'image(r) &" failed. Expected: " & integer'image(g_replicated_value) & " but got: " & integer'image(to_integer(unsigned(s_dout(
((r+1)*bit_width)-1 downto (r*bit_width)
)))), o_test_msg'length, '.');
if g_replicated_value /= unsigned(s_out(((r + 1) * bit_width) - 1 downto (r * bit_width))) then
v_test_msg := pad("Replication #" & integer'image(r) & " failed. Expected: " & integer'image(g_replicated_value) & " but got: " & integer'image(to_integer(unsigned(s_out(((r + 1) * bit_width) - 1 downto (r * bit_width))))), o_test_msg'length, '.');
v_test_pass := FALSE;
REPORT v_test_msg severity failure;
end if;
o_test_msg <= v_test_msg;

o_test_msg <= v_test_msg;
o_test_pass <= v_test_pass;
end loop;

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