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sd kortti debuggausta
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@joukkone
joukkone committed Dec 4, 2024
1 parent 7aed9c3 commit 0542a6a
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Showing 2 changed files with 59 additions and 25 deletions.
80 changes: 56 additions & 24 deletions arch/arm64/src/imx9/imx9_usdhc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@
#include "imx9_clockconfig.h"
#include "imx9_usdhc.h"


#ifdef CONFIG_IMX9_USDHC

/****************************************************************************
Expand All @@ -65,6 +66,7 @@
#endif

#define DCACHE_LINEMASK (ARMV8A_DCACHE_LINESIZE - 1)
#define DCACHE_ALIGN_UP(a) (((a) + DCACHE_LINEMASK) & ~DCACHE_LINEMASK)

#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
# define cache_aligned_alloc(s) kmm_memalign(ARMV8A_DCACHE_LINESIZE,(s))
Expand Down Expand Up @@ -181,8 +183,8 @@ struct imx9_dev_s
/* Event support */

sem_t waitsem; /* Implements event waiting */
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitints; /* Interrupt enables for event waiting */
volatile sdio_eventset_t waitevents; /* Set of events to be waited for */
volatile uint32_t waitints; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
struct wdog_s waitwdog; /* Watchdog that handles event timeouts */

Expand All @@ -197,7 +199,7 @@ struct imx9_dev_s
/* Interrupt mode data transfer support */

uint32_t *buffer; /* Address of current R/W buffer */
size_t remaining; /* Number of bytes remaining in the
volatile size_t remaining; /* Number of bytes remaining in the
* transfer */
uint32_t xfrints; /* Interrupt enables for data transfer */

Expand Down Expand Up @@ -786,16 +788,18 @@ static void imx9_dataconfig(struct imx9_dev_s *priv, bool bwrite,
unsigned int datalen, unsigned int timeout)
{
unsigned int watermark;
uint32_t regval = 0;
//uint32_t regval = 0;

/* Set the data timeout value in the USDHC_SYSCTL field to the selected
* value.
*/

modifyreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET, USDHC_SYSCTL_DTOCV_MASK, timeout << USDHC_SYSCTL_DTOCV_SHIFT);
/*
regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
regval &= ~USDHC_SYSCTL_DTOCV_MASK;
regval |= timeout << USDHC_SYSCTL_DTOCV_SHIFT;
putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET);*/

#if defined(CONFIG_IMX9_USDHC_DMA) && !defined(CONFIG_ARM64_DCACHE_DISABLE)
/* If cache is enabled, and this is an unaligned receive,
Expand Down Expand Up @@ -1122,21 +1126,26 @@ static void imx9_eventtimeout(wdparm_t arg)
{
struct imx9_dev_s *priv = (struct imx9_dev_s *)arg;

uint32_t waite;
DEBUGASSERT(priv != NULL);
DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0);

/* Is a data transfer complete event expected? */

waite = (uint32_t)priv->waitevents;
uint32_t even = (uint32_t)priv->cbevents;
if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0)
{
/* Yes.. Sample registers at the time of the timeout */
mcerr("cdstatus=%02x\n", priv->cdstatus);

imx9_sample(priv, SAMPLENDX_END_TRANSFER);

/* Wake up any waiting threads */

imx9_endwait(priv, SDIOWAIT_TIMEOUT);
mcerr("ERROR: Timeout: remaining: %lu\n", priv->remaining);
mcerr("ERORR: waitevents = 0x%x \n", waite);
mcerr("cbevents = 0x%x\n ", even);
}
}

Expand Down Expand Up @@ -1165,6 +1174,10 @@ static void imx9_endwait(struct imx9_dev_s *priv,

wd_cancel(&priv->waitwdog);

/* disable force clock */

modifyreg32(priv->addr + IMX9_USDHC_VENDOR_OFFSET, (1 << 8) ,0);

/* Disable event-related interrupts */

imx9_configwaitints(priv, 0, 0, wkupevent);
Expand Down Expand Up @@ -1380,9 +1393,11 @@ static int imx9_interrupt(int irq, void *context, void *arg)
{
/* Yes.. mask further interrupts and wake the thread up */

regval = getreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);
regval &= ~USDHC_RESPDONE_INTS;
putreg32(regval, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);
modifyreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET,USDHC_RESPDONE_INTS,0 );

//regval = getreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);
//regval &= ~USDHC_RESPDONE_INTS;
//putreg32(regval, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);

imx9_endwait(priv, SDIOWAIT_RESPONSEDONE);
}
Expand Down Expand Up @@ -1470,6 +1485,14 @@ static void imx9_reset(struct sdio_dev_s *dev)

mcinfo("Reset complete\n");

/* Set VENDOR to default value and reset registers that are not resetted by RSTA */

putreg32(0x20007809, priv->addr + IMX9_USDHC_VENDOR_OFFSET);
putreg32(0, priv->addr + IMX9_USDHC_MMCBOOT_OFFSET);
putreg32(0, priv->addr + IMX9_USDHC_MIX_OFFSET);
putreg32(0, priv->addr + IMX9_USDHC_CLK_TUNE_CTRL_OFFSET);
putreg32(0, priv->addr + IMX9_USDHC_DLL_CONTROL_OFFSET);

/* Make sure that all clocking is disabled */

imx9_clock(dev, CLOCK_SDIO_DISABLED);
Expand Down Expand Up @@ -1839,7 +1862,7 @@ static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
/* Initial ID mode clocking (<400KHz) */

mcinfo("IDMODE\n");
mcerr("IDMODE\n");

/* Put out an additional 80 clocks in case this is a power-up
* sequence.
Expand All @@ -1855,7 +1878,7 @@ static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
/* MMC normal operation clocking */

mcinfo("MMCTRANSFER\n");
mcerr("MMCTRANSFER\n");
regval |= (BOARD_USDHC_MMCMODE_PRESCALER |
BOARD_USDHC_MMCMODE_DIVISOR);
}
Expand All @@ -1865,7 +1888,7 @@ static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
/* SD normal operation clocking (narrow 1-bit mode) */

mcinfo("1BITTRANSFER\n");
mcerr("1BITTRANSFER\n");
regval |= (BOARD_USDHC_SD1MODE_PRESCALER |
BOARD_USDHC_SD1MODE_DIVISOR);
}
Expand All @@ -1875,7 +1898,7 @@ static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
/* SD normal operation clocking (wide 4-bit mode) */

mcinfo("4BITTRANSFER\n");
mcerr("4BITTRANSFER\n");
regval |= (BOARD_USDHC_SD4MODE_PRESCALER |
BOARD_USDHC_SD4MODE_DIVISOR);
}
Expand Down Expand Up @@ -1943,6 +1966,7 @@ static int imx9_attach(struct sdio_dev_s *dev)
putreg32(0, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);
putreg32(USDHC_INT_ALL, priv->addr + IMX9_USDHC_IRQSTAT_OFFSET);


/* Enable SDIO interrupts at the NVIC. They can now be enabled at the
* SDIO controller as needed.
*/
Expand Down Expand Up @@ -2379,7 +2403,7 @@ static int imx9_cancel(struct sdio_dev_s *dev)
struct imx9_dev_s *priv = (struct imx9_dev_s *)dev;

#ifdef CONFIG_IMX9_USDHC_DMA
uint32_t regval;
//uint32_t regval;
#endif

/* Disable all transfer- and event- related interrupts */
Expand All @@ -2402,9 +2426,11 @@ static int imx9_cancel(struct sdio_dev_s *dev)

/* Stop the DMA by resetting the data path */

modifyreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET,0, USDHC_SYSCTL_RSTD );
/*
regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
regval |= USDHC_SYSCTL_RSTD;
putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET);*/
#endif

/* Mark no transfer in progress */
Expand Down Expand Up @@ -2792,6 +2818,11 @@ static void imx9_waitenable(struct sdio_dev_s *dev,
/* Start the watchdog timer */

delay = MSEC2TICK(timeout);

/* Force clock */

modifyreg32(priv->addr + IMX9_USDHC_VENDOR_OFFSET,0 ,(1 << 8));

ret = wd_start(&priv->waitwdog, delay,
imx9_eventtimeout, (wdparm_t)priv);

Expand Down Expand Up @@ -2833,10 +2864,10 @@ static sdio_eventset_t imx9_eventwait(struct sdio_dev_s *dev)
* will be non-zero (and, hopefully, the semaphore count will also be
* non-zero.
*/

/*
DEBUGASSERT((priv->waitevents != 0 && priv->wkupevent == 0) ||
(priv->waitevents == 0 && priv->wkupevent != 0));

*/
/* Loop until the event (or the timeout occurs). Race conditions are
* avoided by calling imx9_waitenable prior to triggering the logic
* that will cause the wait to terminate. Under certain race
Expand Down Expand Up @@ -3075,7 +3106,7 @@ static int imx9_dmarecvsetup(struct sdio_dev_s *dev,
else
{
up_invalidate_dcache((uintptr_t)buffer,
(uintptr_t)buffer + buflen);
(uintptr_t)buffer + DCACHE_ALIGN_UP(buflen));

priv->unaligned_rx = false;
}
Expand Down Expand Up @@ -3285,8 +3316,8 @@ static void imx9_callback(void *arg)
void imx9_usdhc_set_sdio_card_isr(struct sdio_dev_s *dev,
int (*func)(void *), void *arg)
{
irqstate_t flags;
uint32_t regval;
//irqstate_t flags;
// uint32_t regval;
struct imx9_dev_s *priv = (struct imx9_dev_s *)dev;

priv->do_sdio_card = func;
Expand All @@ -3308,11 +3339,12 @@ void imx9_usdhc_set_sdio_card_isr(struct sdio_dev_s *dev,
}
#endif

flags = enter_critical_section();
regval = getreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);
//flags = enter_critical_section();
modifyreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET, USDHC_INT_CINT,priv->cintints );
/*regval = getreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);
regval = (regval & ~USDHC_INT_CINT) | priv->cintints;
putreg32(regval, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);
leave_critical_section(flags);
putreg32(regval, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET);*/
//leave_critical_section(flags);
}

/****************************************************************************
Expand Down
4 changes: 3 additions & 1 deletion drivers/mmcsd/mmcsd_sdio.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,8 @@
#include "mmcsd.h"
#include "mmcsd_sdio.h"

#undef ferr
#define ferr _err
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
Expand Down Expand Up @@ -1527,7 +1529,7 @@ static ssize_t mmcsd_readsingle(FAR struct mmcsd_state_s *priv,
ret = SDIO_DMARECVSETUP(priv->dev, buffer, priv->blocksize);
if (ret != OK)
{
finfo("SDIO_DMARECVSETUP: error %d\n", ret);
ferr("SDIO_DMARECVSETUP: error %d\n", ret);
SDIO_CANCEL(priv->dev);
return ret;
}
Expand Down

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