risc-v/mpfs: Change linker symbols _ssbi_ddr and _esbi_ddr into _ssbi…

…_ram and _esbi_ram The original names are confusing; the symbols' addresses point to the start and end of the sbi executable ram area. This may also reside in l2lim and not in ddr, depending on the configuration, and this is defined in the linker script. Signed-off-by: Jukka Laitinen <[email protected]>
tiiuae · May 16, 2024 · 1079abf · 1079abf
1 parent 2ea821a
commit 1079abf
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Showing 3 changed files with 16 additions and 16 deletions.
diff --git a/arch/risc-v/src/mpfs/mpfs_opensbi.c b/arch/risc-v/src/mpfs/mpfs_opensbi.c
@@ -103,8 +103,8 @@ typedef struct sbi_scratch_holder_s sbi_scratch_holder_t;
 
 extern const uint8_t __mpfs_nuttx_start[];
 extern const uint8_t __mpfs_nuttx_end[];
-extern const uint8_t _ssbi_ddr[];
-extern const uint8_t _esbi_ddr[];
+extern const uint8_t _ssbi_ram[];
+extern const uint8_t _esbi_ram[];
 
 /****************************************************************************
  * Private Function Prototypes
@@ -475,9 +475,9 @@ static void mpfs_opensbi_scratch_setup(uint32_t hartid)
    * them so that OpenSBI has no chance override then.
    */
 
-  g_scratches[hartid].scratch.fw_start = (unsigned long)_ssbi_ddr;
-  g_scratches[hartid].scratch.fw_size  = (unsigned long)_esbi_ddr -
-                                         (unsigned long)_ssbi_ddr;
+  g_scratches[hartid].scratch.fw_start = (unsigned long)_ssbi_ram;
+  g_scratches[hartid].scratch.fw_size  = (unsigned long)_esbi_ram -
+                                         (unsigned long)_ssbi_ram;
 
   g_scratches[hartid].scratch.fw_rw_offset =
       (unsigned long)g_scratches[hartid].scratch.fw_size;

diff --git a/arch/risc-v/src/mpfs/mpfs_opensbi_utils.S b/arch/risc-v/src/mpfs/mpfs_opensbi_utils.S
@@ -43,17 +43,17 @@
 
   /* Add some weak default values to make this compile without */
 
-  .weak  _sbi_zerodev_loadaddr
-  .weak  _ssbi_zerodev
-  .weak  _esbi_zerodev
+  .weak  _sbi_ram_loadaddr
+  .weak  _ssbi_ram
+  .weak  _esbi_ram
 
   /* These are the weak pointless variables, only to get this PR compile */
 
-_sbi_zerodev_loadaddr:
+_sbi_ram_loadaddr:
   .dword  0x0a006000
-_ssbi_zerodev:
+_ssbi_ram:
   .dword  _stext
-_esbi_zerodev:
+_esbi_ram:
   .dword  _stext
 
 /****************************************************************************
@@ -89,9 +89,9 @@ mpfs_opensbi_relocate_from_envm:
 
   /* Relocate the code from eNVM into L2 zero device */
 
-  la    a0, _sbi_zerodev_loadaddr
-  la    a1, _ssbi_zerodev
-  la    a2, _esbi_zerodev
+  la    a0, _sbi_ram_loadaddr
+  la    a1, _ssbi_ram
+  la    a2, _esbi_ram
 .check_if_opensbi_copy_done:
   bge   a1, a2, .opensbi_copy_done
   ld    a3, 0(a0)

diff --git a/boards/risc-v/mpfs/icicle/scripts/ld-envm-opensbi.script b/boards/risc-v/mpfs/icicle/scripts/ld-envm-opensbi.script
@@ -36,12 +36,12 @@ SECTIONS
     PROVIDE(__l2lim_end   = ORIGIN(l2lim) + LENGTH(l2lim));
 
     .text.sbi : {
-      _ssbi_ddr = ABSOLUTE(.);
+      _ssbi_ram = ABSOLUTE(.);
       sbi*
       riscv_atomic*
       riscv_locks*
       riscv_asm*
-      _esbi_ddr = ABSOLUTE(.);
+      _esbi_ram = ABSOLUTE(.);
       . = ALIGN(0x2000);
       . += 16k; /* OpenSBI heap, aligned, at least 16k */
     } > ddr