fixes

Signed-off-by: Jukka Laitinen <[email protected]>
tiiuae · Oct 12, 2024 · 98a4775 · 98a4775
1 parent a8d295c
commit 98a4775
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Showing 3 changed files with 257 additions and 157 deletions.
diff --git a/arch/arm64/src/imx9/Kconfig b/arch/arm64/src/imx9/Kconfig
@@ -1043,23 +1043,24 @@ endmenu # IMX9_ENET
 config IMX9_FLEXCAN
 	bool
 	default n
-        select NET_CAN
-        select NET_CAN_HAVE_CANFD
+	select ARCH_HAVE_CAN_ERRORS
 	select ARCH_HAVE_NETDEV_STATISTICS
+	select CAN
+	select NET_CAN
+	select NET_CAN_HAVE_CANFD
+	select NET_CAN_HAVE_TX_DEADLINE
 
 menu "FLEXCAN Peripherals"
 
 config IMX9_FLEXCAN1
 	bool "FLEXCAN1"
 	default n
 	select IMX9_FLEXCAN
-	select NET_CAN_HAVE_TX_DEADLINE
 
 config IMX9_FLEXCAN2
 	bool "FLEXCAN2"
 	default n
 	select IMX9_FLEXCAN
-	select NET_CAN_HAVE_TX_DEADLINE
 
 if IMX9_FLEXCAN1 || IMX9_FLEXCAN2
 

diff --git a/arch/arm64/src/imx9/hardware/imx9_flexcan.h b/arch/arm64/src/imx9/hardware/imx9_flexcan.h
@@ -58,7 +58,7 @@
 #define IMX9_CAN_ET_OFFSET       0x0078 /* External Timer Register */
 #define IMX9_CAN_FLTC_IE_OFFSET  0x007c /* Fault Confinement Interrupt Enable Register */
 
-#define IMX9_CAN_MB_OFFSET       0x0080 /* CAN MB register */
+#define IMX9_CAN_MB_OFFSET       0x0080 /* CAN MB start */
 #define IMX9_CAN_MB_SIZE         0x0600
 #define IMX9_CAN_MB_END          (IMX9_CAN_MB_OFFSET + IMX9_CAN_MB_SIZE)
 
@@ -71,6 +71,9 @@
 #define IMX9_CAN_TXSMB_OFFSET    0x0ab0 /* Tx_SMB */
 #define IMX9_CAN_RXSMB0_OFFSET   0x0ac0 /* Rx_SMB0 */
 #define IMX9_CAN_TXSMB1_OFFSET   0x0ad0 /* Rx_SMB1 */
+#define IMX9_CAN_TXSMBFD_OFFSET  0x0f28 /* Tx_SMB for can-fd */
+#define IMX9_CAN_RXSMB0FD_OFFSET 0x0f70 /* Rx_SMB0 for can-fd */
+#define IMX9_CAN_TXSMB1FD_OFFSET 0x0fb8 /* Rx_SMB1 for can-fd */
 
 #define IMX9_CAN_MECR_OFFSET     0x0ae0 /* Memory Error Control Register */
 #define IMX9_CAN_ERRIAR_OFFSET   0x0ae4 /* Error Injection Address Register */
@@ -363,6 +366,9 @@
 
 #define CAN_IFLAG3(n)              (1 << (n)) /* Bit n: Buffer MBn Interrupt (95TO64) */
 
+#define IMX9_CAN_FLTC_ATP_IE       (1 << 0)  /* Active to passive interrupt enable */
+#define IMX9_CAN_FLTC_PTA_IE       (1 << 1)  /* Passive to active interrupt enable */
+
 /* TODO: add bit definitions for FLTCONF_IO to ETDC registers when needed */
 
 /* CAN FD Control register */
@@ -424,7 +430,7 @@
 #define CAN_FDCRC_FD_MBCRC(x)      (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
                                             /* Bit 31: Reserved */
 
-/* CAN MB RX codes */
+/* CAN MB TX & RX codes */
 
 #define CAN_RXMB_INACTIVE          0x0        /* MB is inactive */
 #define CAN_RXMB_FULL              0x2        /* MB is full */