riscv/mpfs: Add boilerplate code for SMP

tiiuae · Oct 14, 2024 · ce11a67 · ce11a67
1 parent f7b3d01
commit ce11a67
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Showing 6 changed files with 31 additions and 12 deletions.
diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
@@ -203,6 +203,7 @@ config ARCH_CHIP_MPFS
 	select ARCH_RV_ISA_C
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU
+	select ARCH_HAVE_MULTICPU
 	select ARCH_HAVE_MPU
 	select ARCH_MMU_TYPE_SV39
 	select ARCH_HAVE_ADDRENV

diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_clint.h b/arch/risc-v/src/mpfs/hardware/mpfs_clint.h
@@ -45,4 +45,6 @@
 
 #define MPFS_CLINT_MTIME     (MPFS_CLINT_BASE + 0xbff8)
 
+#define RISCV_IPI            MPFS_CLINT_MSIP0
+
 #endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H */
diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S
@@ -29,6 +29,7 @@
 #include "chip.h"
 #include "mpfs_memorymap.h"
 #include "riscv_internal.h"
+#include "riscv_macros.S"
 
 /****************************************************************************
  * Public Symbols
@@ -183,21 +184,12 @@ __start:
 
   /* Set stack pointer to the idle thread stack */
 
-  la   sp, MPFS_IDLESTACK_TOP
+  riscv_set_inital_sp MPFS_IDLESTACK_BASE, SMP_STACK_SIZE, a0
 
   /* Jump to __mpfs_start with mhartid in a0 */
 
   tail __mpfs_start
 
-  /* We shouldn't return from __mpfs_start
-   * in case of return, loop forever. nop's added so can be seen in debugger
-   */
-
-1:
-  nop
-  nop
-  j 1b
-
   .global _init
   .global _fini
 

diff --git a/arch/risc-v/src/mpfs/mpfs_irq.c b/arch/risc-v/src/mpfs/mpfs_irq.c
@@ -33,6 +33,8 @@
 #include <nuttx/irq.h>
 
 #include "riscv_internal.h"
+#include "riscv_ipi.h"
+
 #include "mpfs.h"
 #include "mpfs_plic.h"
 
@@ -96,6 +98,14 @@ void up_irqinitialize(void)
 
   riscv_exception_attach();
 
+#ifdef CONFIG_SMP
+  /* Clear IPI for CPU0 (aka hart1) */
+
+  riscv_ipi_clear(1);
+
+  up_enable_irq(RISCV_IRQ_SOFT);
+#endif
+
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
 
   /* And finally, enable interrupts */

diff --git a/arch/risc-v/src/mpfs/mpfs_shead.S b/arch/risc-v/src/mpfs/mpfs_shead.S
@@ -95,5 +95,6 @@ __start:
 
   /* Set stack pointer and jump to start */
 
-  la sp, MPFS_IDLESTACK_TOP
-  j __mpfs_start
+  riscv_set_inital_sp MPFS_IDLESTACK_BASE, SMP_STACK_SIZE, a0
+
+  tail __mpfs_start
diff --git a/arch/risc-v/src/mpfs/mpfs_start.c b/arch/risc-v/src/mpfs/mpfs_start.c
@@ -77,6 +77,13 @@ void __mpfs_start(uint64_t mhartid)
       riscv_fpuconfig();
     }
 
+  /* Hart 1 handles the boot, the rest wait */
+
+  if (mhartid > 1)
+    {
+      goto cpux;
+    }
+
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
    * certain that there are no issues with the state of global variables.
    */
@@ -181,6 +188,12 @@ void __mpfs_start(uint64_t mhartid)
 
   showprogress('a');
 
+cpux:
+
+#ifdef CONFIG_SMP
+  riscv_cpu_boot(mhartid);
+#endif
+
   while (true)
     {
       asm("WFI");
Original file line number	Diff line number	Diff line change
Expand Up		@@ -45,4 +45,6 @@

		#define MPFS_CLINT_MTIME (MPFS_CLINT_BASE + 0xbff8)

		#define RISCV_IPI MPFS_CLINT_MSIP0

		#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H */