arm64/imx9: Add GPIO, IOMUX and external interrupt support

This adds memory mapped registers and drivers for digital I/O.

arch/arm64/include/imx9/chip.h

@@ -59,6 +59,8 @@
 
 #define MPID_TO_CLUSTER_ID(mpid)  ((mpid) & ~0xff)
 
+#define IMX9_GPIO_NPORTS          4
+
 #endif
 
 /****************************************************************************

arch/arm64/src/imx9/Kconfig

@@ -28,6 +28,10 @@ config IMX9_UART1
 	select UART1_SERIALDRIVER
 endmenu # iMX Peripheral Selection
 
+config IMX9_GPIO_IRQ
+	bool "GPIO Interrupt Support"
+	default n
+
 config IMX9_PLL
 	bool "PLL setup support (WIP)"
 	default n

arch/arm64/src/imx9/Make.defs

@@ -22,11 +22,15 @@ include common/Make.defs
 
 # i.MX9-specific C source files
 
-CHIP_CSRCS = imx9_boot.c imx9_ccm.c imx9_clockconfig.c
+CHIP_CSRCS = imx9_boot.c imx9_ccm.c imx9_clockconfig.c imx9_gpio.c imx9_iomuxc.c
 
 ifeq ($(CONFIG_ARCH_CHIP_IMX93),y)
   CHIP_CSRCS += imx9_lpuart.c
   ifeq ($(CONFIG_ARCH_EARLY_PRINT),y)
     CHIP_ASRCS = imx93_lowputc.S
   endif
 endif
+
+ifeq ($(CONFIG_IMX9_GPIO_IRQ),y)
+  CHIP_CSRCS += imx9_gpioirq.c
+endif

arch/arm64/src/imx9/chip.h

@@ -29,6 +29,8 @@
 
 #ifndef __ASSEMBLY__
 #  include <nuttx/arch.h>
+#  include <arch/irq.h>
+#  include <arch/imx9/chip.h>
 #endif
 
 /****************************************************************************

arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h

@@ -0,0 +1,59 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H
+#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "imx93_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define IMX9_GPIO_VERID_OFFSET          (0x0000) /* Version ID */
+#define IMX9_GPIO_PARAM_OFFSET          (0x0004) /* Parameter */
+#define IMX9_GPIO_LOCK_OFFSET           (0x000c) /* Lock */
+#define IMX9_GPIO_PCNS_OFFSET           (0x0010) /* Pin Control Nonsecure */
+#define IMX9_GPIO_ICNS_OFFSET           (0x0014) /* Interrupt Control Nonsecure */
+#define IMX9_GPIO_PCNP_OFFSET           (0x0018) /* Pin Control Nonprivilege */
+#define IMX9_GPIO_ICNP_OFFSET           (0x001c) /* Interrupt Control Nonprivilege */
+#define IMX9_GPIO_PDOR_OFFSET           (0x0040) /* Port Data Output */
+#define IMX9_GPIO_PSOR_OFFSET           (0x0044) /* Port Set Output */
+#define IMX9_GPIO_PCOR_OFFSET           (0x0048) /* Port Clear Output */
+#define IMX9_GPIO_PTOR_OFFSET           (0x004c) /* Port Toggle Output */
+#define IMX9_GPIO_PDIR_OFFSET           (0x0050) /* Port Data Input */
+#define IMX9_GPIO_PDDR_OFFSET           (0x0054) /* Port Data Direction */
+#define IMX9_GPIO_PIDR_OFFSET           (0x0058) /* Port Input Disable */
+#define IMX9_GPIO_P0DR_OFFSET           (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */
+#define IMX9_GPIO_ICR0_OFFSET           (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */
+#define IMX9_GPIO_GICLR_OFFSET          (0x0100) /* Global Interrupt Control Low */
+#define IMX9_GPIO_GICHR_OFFSET          (0x0104) /* Global Interrupt Control High */
+#define IMX9_GPIO_ISFR0_OFFSET          (0x0120) /* Interrupt Status Flag */
+#define IMX9_GPIO_ISFR1_OFFSET          (0x0124) /* Interrupt Status Flag */
+
+#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H */

arch/arm64/src/imx9/hardware/imx9_gpio.h

@@ -0,0 +1,106 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx9_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H
+#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_IMX93)
+#  include "hardware/imx93/imx93_gpio.h"
+#else
+#  error Unrecognized i.MX9 architecture
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define GPIO1                           0      /* Port 1 index */
+#define GPIO2                           1      /* Port 2 index */
+#define GPIO3                           2      /* Port 3 index */
+#define GPIO4                           3      /* Port 4 index */
+#define GPIO5                           4      /* Port 5 index */
+#define GPIO6                           5      /* Port 6 index */
+#define GPIO7                           6      /* Port 7 index */
+#define GPIO8                           7      /* Port 8 index */
+#define GPIO9                           8      /* Port 9 index */
+#define GPIO10                          9      /* Port 10 index */
+#define GPIO11                          10     /* Port 11 index */
+#define GPIO12                          11     /* Port 12 index */
+#define GPIO13                          12     /* Port 13 index */
+
+#define IMX9_GPIO_NPINS                 32     /* Up to 32 pins per port */
+
+/* Register bit definitions *************************************************/
+
+/* Most registers are laid out simply with one bit per pin */
+
+#define GPIO_PIN(n)                     (1 << (n)) /* Bit n: Pin n, n=0-31 */
+
+/* ICRN Register */
+
+#define IMX9_GPIO_ICRN_ISF              (1 << 24) /* Bit 24: Interrupt Status Flag */
+#define IMX9_GPIO_ICRN_LK               (1 << 23) /* Bit 23: Lock Register */
+#define IMX9_GPIO_ICRN_IRQS             (1 << 20) /* Bit 20: Configures the selected interrupt, or DMA request. */
+#define IMX9_GPIO_ICRN_SHIFT            (16)      /* Bits 16-19:  Interrupt Configuration */
+#define IMX9_GPIO_ICRN_MASK             (0xf << IMX9_GPIO_ICRN_SHIFT)
+#  define IMX9_GPIO_ICRN_DISABLED       (0 << IMX9_GPIO_ICRN_SHIFT)  /* Interrupt Status Flag (ISF) is disabled */
+#  define IMX9_GPIO_ICRN_DMARISING      (1 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag and DMA request on rising edge */
+#  define IMX9_GPIO_ICRN_DMAFALLING     (2 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag and DMA request on falling edge */
+#  define IMX9_GPIO_ICRN_DMABOTH        (3 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag and DMA request on either edge */
+#  define IMX9_GPIO_ICRN_ISFRISING      (5 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag sets on rising edge */
+#  define IMX9_GPIO_ICRN_ISFFALLING     (6 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag sets on falling edge */
+#  define IMX9_GPIO_ICRN_ISFBOTH        (7 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag sets on either edge */
+#  define IMX9_GPIO_ICRN_ZERO           (8 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag and Interrupt when logic 0 */
+#  define IMX9_GPIO_ICRN_RISING         (9 << IMX9_GPIO_ICRN_SHIFT)  /* ISF flag and Interrupt on rising-edge */
+#  define IMX9_GPIO_ICRN_FALLING        (10 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on falling-edge */
+#  define IMX9_GPIO_ICRN_BOTH           (11 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on either edge */
+#  define IMX9_GPIO_ICRN_ONE            (12 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 1 */
+
+/* Global Interrupt Control Low Register */
+
+#define IMX9_GPIO_GICLR_GIWD_SHIFT      (0)       /* Bits 0-15: Global Interrupt Write Data */
+#define IMX9_GPIO_GICLR_GIWD_MASK       (0xffff << IMX9_GPIO_GICLR_GIWD_SHIFT)
+#  define IMX9_GPIO_GICLR_GIWD_PIN(n)   ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWD_SHIFT) /* Pin n=0..15 */
+
+#define IMX9_GPIO_GICLR_GIWE_SHIFT      (16)      /* Bits 16-31: Global Interrupt Write Enable */
+#define IMX9_GPIO_GICLR_GIWE_MASK       (0xffff << IMX9_GPIO_GICLR_GIWE_SHIFT)
+#  define IMX9_GPIO_GICLR_GIWE_PIN(n)   ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWE_SHIFT) /* Pin n=0..15 */
+
+/* Global Interrupt Control High Register */
+
+#define IMX9_GPIO_GICHR_GIWD_SHIFT      (0)       /* Bits 0-15: Global Interrupt Write Data */
+#define IMX9_GPIO_GICHR_GIWD_MASK       (0xffff << IMX9_GPIO_GICHR_GIWD_SHIFT)
+#  define IMX9_GPIO_GICHR_GIWD_PIN(n)   ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWD_SHIFT) /* Pin n=16..31 */
+
+#define IMX9_GPIO_GICHR_GIWE_SHIFT      (16)      /* Bits 16-31: Global Interrupt Write Enable */
+#define IMX9_GPIO_GICHR_GIWE_MASK       (0xffff << IMX9_GPIO_GICHR_GIWE_SHIFT)
+#  define IMX9_GPIO_GICHR_GIWE_PIN(n)   ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWE_SHIFT) /* Pin n=16..31 */
+
+/* Interrupt Status Flag Register */
+
+#define IMX9_GPIO_ISFR(n)               (1 << (n))  /* Interrupt Status Flag, n=0-31 */
+
+#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H */

arch/arm64/src/imx9/hardware/imx9_iomuxc.h

@@ -0,0 +1,104 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx9_iomuxc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H
+#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_IMX93)
+#  include "hardware/imx93/imx93_iomux.h"
+#else
+#  error Unrecognized i.MX9 architecture
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Pad muxing */
+
+#define IOMUXC_MUX_MODE_SHIFT   (0)   /* MODE: pin alternate function */
+#define IOMUXC_MUX_MODE_MASK    (0x03 << IOMUXC_MUX_MODE_SHIFT)
+#define IOMUXC_MUX_MODE_ALT0    (0 << IOMUXC_MUX_MODE_SHIFT)
+#define IOMUXC_MUX_MODE_ALT1    (1 << IOMUXC_MUX_MODE_SHIFT)
+#define IOMUXC_MUX_MODE_ALT2    (2 << IOMUXC_MUX_MODE_SHIFT)
+#define IOMUXC_MUX_MODE_ALT3    (3 << IOMUXC_MUX_MODE_SHIFT)
+#define IOMUXC_MUX_MODE_ALT4    (4 << IOMUXC_MUX_MODE_SHIFT)
+#define IOMUXC_MUX_MODE_ALT5    (5 << IOMUXC_MUX_MODE_SHIFT)
+#define IOMUXC_MUX_MODE_ALT6    (6 << IOMUXC_MUX_MODE_SHIFT)
+
+#define IOMUXC_MUX_SION_SHIFT   (4)   /* SION: Force input path */
+#define IPMUXC_MUX_SION_MASK    (0x01 << IOMUXC_MUX_SION_SHIFT)
+#define IOMUXC_MUX_SION_OFF     (0 << IOMUXC_MUX_SION_SHIFT)
+#define IOMUXC_MUX_SION_ON      (1 << IOMUXC_MUX_SION_SHIFT)
+
+/* Pad control */
+
+#define IOMUXC_PAD_DSE_SHIFT    (1)   /* DSE: Drive strength */
+#define IOMUXC_PAD_DSE_MASK     (0x3f << IOMUXC_PAD_DSE_SHIFT)
+#define IOMUXC_PAD_DSE_X0       (0x00 << IOMUXC_PAD_DSE_SHIFT)
+#define IOMUXC_PAD_DSE_X1       (0x01 << IOMUXC_PAD_DSE_SHIFT)
+#define IOMUXC_PAD_DSE_X2       (0x03 << IOMUXC_PAD_DSE_SHIFT)
+#define IOMUXC_PAD_DSE_X3       (0x07 << IOMUXC_PAD_DSE_SHIFT)
+#define IOMUXC_PAD_DSE_X4       (0x0f << IOMUXC_PAD_DSE_SHIFT)
+#define IOMUXC_PAD_DSE_X5       (0x1f << IOMUXC_PAD_DSE_SHIFT)
+#define IOMUXC_PAD_DSE_X6       (0x3f << IOMUXC_PAD_DSE_SHIFT)
+
+#define IOMUXC_PAD_FSEL_SHIFT   (7)   /* FSEL: Slew rate control */
+#define IOMUXC_PAD_FSEL_MASK    (0x02 << IOMUXC_PAD_FSEL_SHIFT)
+#define IOMUXC_PAD_FSEL_SLOW    (0 << IOMUXC_PAD_FSEL_SHIFT)
+#define IOMUXC_PAD_FSEL_SSLOW   (1 << IOMUXC_PAD_FSEL_SHIFT)   /* Slightly slow */
+#define IOMUXC_PAD_FSEL_SFAST   (2 << IOMUXC_PAD_FSEL_SHIFT)   /* Slightly fast */
+#define IOMUXC_PAD_FSEL_FAST    (3 << IOMUXC_PAD_FSEL_SHIFT)
+
+#define IOMUXC_PAD_PU_SHIFT     (9)   /* PU: Pull-up */
+#define IOMUXC_PAD_PU_MASK      (0x01 << IOMUXC_PAD_PU_SHIFT)
+#define IOMUXC_PAD_PU_OFF       (0 << IOMUXC_PAD_PU_SHIFT)
+#define IOMUXC_PAD_PU_ON        (1 << IOMUXC_PAD_PU_SHIFT)
+
+#define IOMUXC_PAD_PD_SHIFT     (10)  /* PD: Pull-down */
+#define IOMUXC_PAD_PD_MASK      (0x01 << IOMUXC_PAD_PD_SHIFT)
+#define IOMUXC_PAD_PD_OFF       (0 << IOMUXC_PAD_PD_SHIFT)
+#define IOMUXC_PAD_PD_ON        (1 << IOMUXC_PAD_PD_SHIFT)
+
+#define IOMUXC_PAD_OD_SHIFT     (11)  /* OD: Open-drain */
+#define IOMUXC_PAD_OD_MASK      (0x01 << IOMUXC_PAD_OD_SHIFT)
+#define IOMUXC_PAD_OD_DISABE    (0 << IOMUXC_PAD_OD_SHIFT)
+#define IOMUXC_PAD_OD_ENABLE    (1 << IOMUXC_PAD_OD_SHIFT)
+
+#define IOMUXC_PAD_HYS_SHIFT    (12)  /* HYS: Enable schmitt-trigger on input */
+#define IOMUXC_PAD_HYS_MASK     (0x01 << IOMUXC_PAD_HYS_SHIFT)
+#define IOMUXC_PAD_HYS_ST_OFF   (0 << IOMUXC_PAD_HYS_SHIFT)   /* Schmitt-trigger off */
+#define IOMUXC_PAD_HYS_ST_ON    (1 << IOMUXC_PAD_HYS_SHIFT)   /* Schmitt-trigger on */
+
+#define IOMUXC_PAD_APC_SHIFT    (24)  /* APC: Access control */
+#define IOMUXC_PAD_APC_MASK     (0xff << IOMUXC_PAD_APC_SHIFT)
+
+/* Daisy chain control, 2 bits seems to be enough */
+
+#define IOMUXC_DSY_SHIFT        (0)
+#define IOMUXC_DSY_MASK         (0x03 << IOMUXC_DSY_SHIFT)
+
+#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H */

arch/arm64/src/imx9/hardware/imx9_pinmux.h

@@ -0,0 +1,36 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx9_pinmux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H
+#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_IMX93)
+#  include "hardware/imx93/imx93_pinmux.h"
+#else
+#  error Unrecognized i.MX9 architecture
+#endif
+
+#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H */