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arch/pmp: Pull some changes from upstream #176

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merged 3 commits into from
Oct 24, 2023
Merged

arch/pmp: Pull some changes from upstream #176

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d416a1b
riscv/riscv_pmp.c: fix broken TOR checks
eenurkka Sep 20, 2023
651a2fd
arch/risc-v: Remove unnecessary PMP kconfig options
pussuw Oct 23, 2023
1624932
arch/risc-v: Simplify pmp_check_region_attrs sanity-checks
pussuw Oct 23, 2023
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24 changes: 0 additions & 24 deletions arch/risc-v/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -149,7 +149,6 @@ config ARCH_CHIP_MPFS
select ARCH_HAVE_SPI_CS_CONTROL
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_S_MODE
select PMP_HAS_LIMITED_FEATURES
select ONESHOT
select ALARM_ARCH
---help---
Expand Down Expand Up @@ -321,29 +320,6 @@ config ARCH_USE_S_MODE
and/or U-mode (in case of separate kernel-/userspaces). This provides
an option to run the kernel in S-mode, if the target supports it.

# MPU has certain architecture dependent configurations, which are presented
# here. Default is that the full RISC-V PMP specification is supported.

config PMP_HAS_LIMITED_FEATURES
bool
default n

config ARCH_MPU_MIN_BLOCK_SIZE
int "Minimum MPU (PMP) block size"
default 4 if !PMP_HAS_LIMITED_FEATURES

config ARCH_MPU_HAS_TOR
bool "PMP supports TOR"
default y if !PMP_HAS_LIMITED_FEATURES

config ARCH_MPU_HAS_NO4
bool "PMP supports NO4"
default y if !PMP_HAS_LIMITED_FEATURES

config ARCH_MPU_HAS_NAPOT
bool "PMP supports NAPOT"
default y if !PMP_HAS_LIMITED_FEATURES

choice
prompt "Toolchain Selection"
default RISCV_TOOLCHAIN_GNU_RV64
Expand Down
156 changes: 40 additions & 116 deletions arch/risc-v/src/common/riscv_pmp.c
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@
#include <nuttx/compiler.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/lib/math32.h>

#include "riscv_internal.h"

Expand All @@ -47,18 +48,6 @@
#define PMP_XLEN (64)
#endif

/* Minimum supported block size */

#if !defined CONFIG_ARCH_MPU_MIN_BLOCK_SIZE
#define MIN_BLOCK_SIZE (PMP_XLEN / 8)
#else
#define MIN_BLOCK_SIZE CONFIG_ARCH_MPU_MIN_BLOCK_SIZE
#endif

/* Address and block size alignment mask */

#define BLOCK_ALIGN_MASK (MIN_BLOCK_SIZE - 1)

#define PMP_CFG_BITS_CNT (8)
#define PMP_CFG_FLAG_MASK ((uintptr_t)0xFF)

Expand Down Expand Up @@ -100,77 +89,6 @@ typedef struct pmp_entry_s pmp_entry_t;
* Private Functions
****************************************************************************/

/****************************************************************************
* Name: log2ceil
*
* Description:
* Calculate the up-rounded power-of-two for input.
*
* Input Parameters:
* size - The size of the PMP region.
*
* Returned Value:
* Power-of-two for argument, rounded up.
*
****************************************************************************/

static uintptr_t log2ceil(uintptr_t size)
{
uintptr_t pot = 0;

for (size = size - 1; size > 1; size >>= 1)
{
pot++;
}

return pot;
}

/****************************************************************************
* Name: pmp_check_addrmatch_type
*
* Description:
* Test if an address matching type is supported by the architecture.
*
* Input Parameters:
* type - The type to test.
*
* Returned Value:
* true if it is, false otherwise.
*
****************************************************************************/

static bool pmp_check_addrmatch_type(uintptr_t type)
{
/* Parameter is potentially unused */

UNUSED(type);
#ifdef CONFIG_ARCH_MPU_HAS_TOR
if (type == PMPCFG_A_TOR)
{
return true;
}

#endif
#ifdef CONFIG_ARCH_MPU_HAS_NO4
if (type == PMPCFG_A_NA4)
{
return true;
}

#endif
#ifdef CONFIG_ARCH_MPU_HAS_NAPOT
if (type == PMPCFG_A_NAPOT)
{
return true;
}
#endif

/* None of the supported types match */

return false;
}

/****************************************************************************
* Name: pmp_check_region_attrs
*
Expand All @@ -180,6 +98,7 @@ static bool pmp_check_addrmatch_type(uintptr_t type)
* Input Parameters:
* base - The base address of the region.
* size - The memory length of the region.
* type - Address matching type.
*
* Returned Value:
* true if it is, false otherwise.
Expand All @@ -189,42 +108,54 @@ static bool pmp_check_addrmatch_type(uintptr_t type)
static bool pmp_check_region_attrs(uintptr_t base, uintptr_t size,
uintptr_t type)
{
/* Check that the size is not too small */
switch (type)
{
case PMPCFG_A_TOR:

if (size < MIN_BLOCK_SIZE)
{
return false;
}
/* For TOR any size is good, but alignment requirement stands */

/* Check that the base address is aligned properly */
if ((base & 0x03) != 0)
{
return false;
}

if ((base & BLOCK_ALIGN_MASK) != 0)
{
return false;
}
break;

/* Check that the size is aligned properly */
case PMPCFG_A_NA4:

if ((size & BLOCK_ALIGN_MASK) != 0)
{
return false;
}
/* For NA4 only size 4 is good, and base must be aligned */

/* Perform additional checks on base and size for NAPOT area */
if ((base & 0x03) != 0 || size != 4)
{
return false;
}

if (type == PMPCFG_A_NAPOT)
{
/* Get the power-of-two for size, rounded up */
break;

uintptr_t pot = log2ceil(size);
case PMPCFG_A_NAPOT:
{
/* For NAPOT, both base and size must be properly aligned */

if ((base & ((UINT64_C(1) << pot) - 1)) != 0)
{
/* The start address is not properly aligned with size */
if ((base & 0x07) != 0 || size < 8)
{
return false;
}

return false;
}
}
/* Get the power-of-two for size, rounded up */

if ((base & ((UINT64_C(1) << LOG2_CEIL(size)) - 1)) != 0)
{
/* The start address is not properly aligned with size */

return false;
}
}

break;

default:
break;
}

return true;
}
Expand Down Expand Up @@ -489,13 +420,6 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
uintptr_t cfg = 0;
uintptr_t type = (attr & PMPCFG_A_MASK);

/* Check that the architecture supports address matching type */

if (pmp_check_addrmatch_type(type) == false)
{
return -EINVAL;
}

/* Check the region attributes */

if (pmp_check_region_attrs(base, size, type) == false)
Expand Down
14 changes: 0 additions & 14 deletions arch/risc-v/src/mpfs/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -893,20 +893,6 @@ config MPFS_CORERMII_ADDRESS
default 1
depends on MPFS_HAVE_CORERMII

# Override the default values for MPU / PMP parameters here

config ARCH_MPU_MIN_BLOCK_SIZE
default 4096

config ARCH_MPU_HAS_TOR
default n

config ARCH_MPU_HAS_NO4
default n

config ARCH_MPU_HAS_NAPOT
default y

config MPFS_CRYPTO
bool "Enable MPFS HW crypto"
default n
Expand Down