risc-v/mpfs: emmcsd: enforce HS DDR mode #197
Conversation
arch/risc-v/src/mpfs/mpfs_emmcsd.c
Outdated
|
|
||
| mpfs_setclkrate(priv, clckr); | ||
|
|
||
| /* REVISIT: This should really be a separate configuration procedure */ |
There was a problem hiding this comment.
THe comment is now misplaced. The comment is supposed to indicate that the 8-bit mode implementation needs
revisiting, I think that mode should be selected by the upper level driver?
There was a problem hiding this comment.
Yes, but not sure there's support, it would need to be added in emmcsd.c file. Eg. would need to change that file.
But even if proper support was in emmcsd.c; reading out the CSD infos would probably put the clock too high for Saluki-v2 devices at least, if the limiting factor was due to the muxers or something - not the info at the mmc card itself.
There was a problem hiding this comment.
Yes I know there is no upper level driver support, this is why the 8-bit mode is kind of hacked here
Previously, address 0x03b70000u was written with shift bits that only changed the bit width, not the mode. HS mode is changed via 0x03B90100, which is required, according to Jedec specs, for DDR mode. HS mode was not applied before. Enforce DDR mode (50 MHz) for now. The real boost, however, comes from removing the DMA limitation at 0x08xxxxxx address space, which now seems unnecessary. Signed-off-by: Eero Nurkkala <[email protected]>
Previously, address 0x03b70000u was written with shift bits that only changed the bit width, not the mode. HS mode is changed via 0x03B90100, which is required, according to Jedec specs, for DDR mode. HS mode was not applied before. Enforce DDR mode (50 MHz) for now.
The real boost, however, comes from removing the DMA limitation at 0x08xxxxxx address space, which now seems unnecessary.
Summary
This boosts the emmc write speed to approximately 3x, near 5M / sec. The greatest boost is from removing the DMA limitation, which for some reason, just works with DMA.
Impact
Testing
Only saluki-v2