DO NOT MERGE: introduce codeQL issue #247
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Add release notes for 12.4.0 release Signed-off-by: Alin Jerpelea <[email protected]>
- boots from eNVM - uses lim memory for RAM - has console on uart 0 - has procfs enabled - has most of nsh commands enabled Signed-off-by: Jukka Laitinen <[email protected]>
- Change git repository urls to point to our tiiuae repos for nuttx & nuttx apps - Remove most of the the build steps, leave just arm-12 and riscv; arm-12 has a build for stm32f7, and riscv for mpfs Signed-off-by: Jukka Laitinen <[email protected]>
…ptimized version in tiiuae repo Signed-off-by: Jukka Laitinen <[email protected]>
…iver to re-initialize on rx timeout If the interface is UP, and no packets are received in 30s, re-initialize the interface by calling the already implemented mpfs_txtimeout_expiry. This is a temporary workaround for a bug where IF might be UP and working but packets can only be transmitted. Receive side just doesn't work at all. The original bug can be re-produced easily by disconnecting and reconnecting the ethernet cable while the IF is up. Signed-off-by: Jukka Laitinen <[email protected]>
SD-card clock speed is just forced to 50MHz. Note that to be correct, one should first set the SD-card into high-speed mode, but currently NuttX doesn't support this. With our cards, just setting the interface to 50MHz seems to work fine, and it removes the issue with 25MHZ clock causing disturbance on GPS bands. Typically cards which support high-speed mode just work with 50MHz interface clock. This patch should be reverted when the NuttX supports high-speed mode, and we can properly set it. Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
…ootloader This removes the need to have all the DDR/clock configuration related "LIBERODEFS" flags defined, when not building a standalone/coldboot configuration All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER Signed-off-by: Jukka Laitinen <[email protected]>
This is not the correct way to do this, but it gives a nice perf. boost
Disable macOS builds for now.
All other commands are disabled in send_recv(). Signed-off-by: Jani Paalijarvi <[email protected]>
…ef and forward declare devif_loopback Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
… that takes care of the need for loopback
Enable LINUX_ON_HART4 in rpmsg-ch2 defconfig of ICICLE board. Remove LINUX_ON_HART4 config from rpmsg-ch1 defconfig of ICICLE board.
Fix build warning when CONFIG_STM32F7_AUTONEG is not set Signed-off-by: Jukka Laitinen <[email protected]>
…ved IO area in protected build Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
Just a temporary patch, need to implement some kind of scalable solution for this. It might be a good idea to map something else for the user to avoid using ecall to enter the kernel for simple reads ? Also, increase the L3 table size
There is no make step executed for this directory before the Kconfigure, so all Kconfig's just need to be in-tree Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
sendfifo() function need enable BWR_IE before checking if BWE is enabled to avoid BWE to be activated between the BWE check and BWR interrupt enabling, which causes the interrupt to be missed and Data Timeout error.
This adds memory mapped registers and drivers for digital I/O.
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for generating PWM period and the rest of the timers to generate PWM duty cycles. This means that the period has to be the same for every PWM generated from one FLEXIO block, but this way we can get 16-bit resolution for the PWM signals. For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means that by using this driver one can get 7 PWM outputs from one block. This driver can be later extended to have configuration options to use all 8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by using an external trigger from an LPIT. Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
…ase address macros Signed-off-by: Jukka Laitinen <[email protected]>
This is a modified version from imxrt driver, which has the same controller. Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
…e width Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
The original assumption was that the interrupt numbers are divided so that 16 pins from 1 port are handled by a single interrupt source. So source 0 would handle pins 0-15 and source 1 would handle pins 16-31. This assumption is wrong, each pin has two sources, thus there are two interrupt lines for each pin. The driver uses source 0, and leaves source 1 disabled.
Signed-off-by: Jukka Laitinen <[email protected]>
Signed-off-by: Jukka Laitinen <[email protected]>
… GPIO_IO24 Signed-off-by: Jukka Laitinen <[email protected]>
These are needed by drivers
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:
imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
54 | }
|
Add an uart driver supporting LPUART1-8, dma, flow control, tc etc. Signed-off-by: Jukka Laitinen <[email protected]>
… PWM registration Fix typo causing TPM PWM not initializing on EVK board Signed-off-by: Jukka Laitinen <[email protected]>
fix Relative file path does not match actual file.
Initialize the pin interrupt support during boot
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable should not be shifted right.
Add driver for LPSPI Co-authored-by: Jukka Laitinen <[email protected]>
…cache management Align all the dtd and dqh on cache line boundaries and clean up the cache management Signed-off-by: Jukka Laitinen <[email protected]>
…RMV8A_DCACHE_LINESIZE Signed-off-by: Jukka Laitinen <[email protected]>
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| @@ -794,6 +794,8 @@ | |||
| cmdlen++; | |||
| g_command[cmdlen] = '\0'; | |||
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| ret = system(g_command); | |||
Check failure
Code scanning / CodeQL
Uncontrolled data used in OS command Critical
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This PR tries to create a new coding issue that CodeQL should be able to find.
It is done to demonstrate the CodeQL functionality