i.MX93 uSDHC #252
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i.MX93 uSDHC #252
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pussuw
reviewed
May 3, 2024
pussuw
reviewed
May 3, 2024
jlaitine
reviewed
May 3, 2024
jlaitine
reviewed
May 3, 2024
| /* Save the source buffer information for use by the interrupt handler */ | ||
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| #if !defined(CONFIG_ARM64_DCACHE_DISABLE) | ||
| priv->unaligned_rx = false; |
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This looks odd, why set the unaligned_rx here in sendsetup?
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actually this is needed here.. clears the flag before a new transfer.
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Nope, this is dmasendsetup. The flag is correctly initialized in dmarecvsetup. This flag has nothing to do with dma sending.
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If I remove the flag DMA transfers fail :)
jlaitine
reviewed
May 3, 2024
Signed-off-by: Jani Paalijarvi <[email protected]>
Fix a bug which causes that 1-bit mode is always selected. This happens even if the driver sets SDIO_CAPS_4BIT capability in case of the card and the host support 1- and 4-bit wide bus. Signed-off-by: Jani Paalijarvi <[email protected]>
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Did some code cleanup.. |
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Closing this. We will take these and couple of other changes from the upstream. |
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Summary
Impact
Testing