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arch/risc-v/src/mpfs/mpfs_corespi.c: Add support for multiple bit widths #326

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merged 1 commit into from
Dec 11, 2024

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jlaitine
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The corespi fpga block supports just one frame length, which is defined when the block is instantiated on the FPGA.

This adds support for emulating different frame lengths if they are multiples of 8-bit. That is, with 8-bit corespi one can do 8,16 and 24-bit transfers.

This is implemented by simply writing several 8-bit frames for a single word when needed.

The corespi fpga block supports just one frame length, which is defined when
the block is instantiated on the FPGA.

This adds support for emulating different frame lengths if they are multiples
of 8-bit. That is, with 8-bit corespi one can do 8,16 and 24-bit transfers.

This is implemented by simply writing several 8-bit frames for a single word
when needed.

Signed-off-by: Jukka Laitinen <[email protected]>
@jlaitine jlaitine force-pushed the corespi_enable_16_bit branch from 8d96bf0 to f29c916 Compare December 11, 2024 10:35
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LGTM, very confusing / hard to follow logic but seems to work

@jlaitine jlaitine merged commit 6819583 into master Dec 11, 2024
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@jlaitine jlaitine deleted the corespi_enable_16_bit branch December 11, 2024 12:04
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2 participants