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Coremmc performance workaround #352

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Feb 13, 2025
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6 changes: 6 additions & 0 deletions arch/risc-v/src/mpfs/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -442,6 +442,12 @@ config MPFS_COREMMC_IRQNUM
range 0 63
depends on MPFS_COREMMC

config MPFS_FPGA_FIC0_CLK_FREQ
int "FIC0 clk freq"
default 125000000
---help---
Frequency of FPGA FIC0 clock.

config MPFS_TAMPER
bool "Tamper detection"
default n
Expand Down
19 changes: 7 additions & 12 deletions arch/risc-v/src/mpfs/mpfs_coremmc.c
Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@

/* Clocks and timing */

#define MPFS_FPGA_FIC0_CLK (50000000)
#define MPFS_FPGA_FIC0_CLK (CONFIG_MPFS_FPGA_FIC0_CLK_FREQ)

#define COREMMC_CMDTIMEOUT (100000)
#define COREMMC_LONGTIMEOUT (100000000)
Expand Down Expand Up @@ -989,7 +989,7 @@ static bool mpfs_device_reset(struct sdio_dev_s *dev)

/* Store fifo size for later to check no fifo overruns occur */

fifo_size = ((getreg8(MPFS_COREMMC_VR) >> 2) & 0x3);
fifo_size = ((getreg8(MPFS_COREMMC_VR) >> 4) & 0x3);
if (fifo_size == 0)
{
priv->fifo_depth = 512;
Expand Down Expand Up @@ -1072,6 +1072,11 @@ static sdio_capset_t mpfs_capabilities(struct sdio_dev_s *dev)
caps |= SDIO_CAPS_1BIT_ONLY;
}

if (((getreg8(MPFS_COREMMC_VR) >> 2) & 3) == 0x01)
{
caps |= SDIO_CAPS_4BIT;
}

return caps;
}

Expand Down Expand Up @@ -1337,16 +1342,6 @@ static int mpfs_sendcmd(struct sdio_dev_s *dev, uint32_t cmd,
struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev;
uint32_t cmdidx;

mpfs_reset_lines(priv);

/* Check if command / data lines are busy */

if (mpfs_check_lines_busy(priv))
{
mcerr("Busy!\n");
return -EBUSY;
}

/* Clear all status interrupts */

mpfs_putreg8(priv, COREMMC_ALL_ICR, MPFS_COREMMC_ICR);
Expand Down
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