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nexys4ddr

Here are 35 public repositories matching this topic...

shinde-shantanu / FPGA_TDC

Time to Digital Converter on an FPGA

fpga verilog xilinx-vivado nexys4ddr

Updated Oct 8, 2020
VHDL

santifs / ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

vhdl ultrasonic-sensor xilinx-fpga 7segment vhdl-modules vhdl-code nexys4ddr parking-sensor fpga-programming

Updated Dec 5, 2019
VHDL

zhongyuchen / mips-32bit

Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board

fpga mips verilog vivado nexys4ddr

Updated Sep 15, 2022
Verilog

g0kul / Game-of-Balance-on-Nexys4DDR

Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board.

c fpga verilog microblaze nexys4ddr game-of-balance softprocessor

Updated Jan 27, 2018
VHDL

yidiwang21 / Nexys-4-Projects

Mini projects based on Xilinx Nexys 4 DDR

fpga verilog nexys4ddr

Updated Oct 14, 2017
VHDL

7enTropy7 / Artix_7

My experiments with Nexys4 DDR Artix-7 FPGA Board

verilog nexys4ddr verilog-project fpga-programming artix-7

Updated Oct 1, 2020
Verilog

nickschiffer / parallel_unsigned_integer_multiplier

Xilinx Vivado Project

fpga verilog vivado nexys4ddr

Updated Mar 20, 2018
Verilog

luminoso / cr-countones

Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs

fpga finite-state-machine xilinx vivado xilinx-fpga xilinx-vivado nexys4ddr

Updated Aug 30, 2017
VHDL

Louis-GUENEGO / NEXYS4ddr_microphone

An audio project with the NEXYS 4 ddr

audio vhdl microphone enseirb-matmeca oversampling pdm reverberation undersampling nexys4ddr automatic-volume

Updated Apr 17, 2022
VHDL

SnrNotHere16 / FPGADivisionFloatingPoint

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

c sdk fpga zynq verilog xilinx floating-point hdl division xilinx-vivado microblaze zynq-7000 nexys4ddr floating-ip artix-7 floating-point-conversion

Updated Apr 5, 2022
VHDL

edw4rdyao / sdcard_digital_recognition

FPGA based SD card reads and displays pictures and performs digital recognition experiments.

fpga verilog sdcard digital-recognition nexys4ddr

Updated Sep 27, 2021
Verilog

nickschiffer / fsm_calculator

A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board

fsm fpga verilog xilinx-vivado nexys4ddr

Updated Dec 9, 2018
Verilog

sromerop / ArtificialNeuron

It is my Final Degree Project of Grado de Tecnologías y Servicios de Telecomunicación in Universidad Politécnica de Madrid

fpga vhdl neural-networks artificial-neural-networks low-latency perceptron upm vhdl-code nexys4ddr artificial-neuron

Updated Jan 24, 2019
VHDL

SnrNotHere16 / Asynchronous-FIFO

An FPGA implementation of Cummings' Asynchronous FIFO

Updated Apr 14, 2022
SystemVerilog

santifs / simon-game-vhdl

VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.

vhdl simon-game finite-state-machine xilinx led-matrix-displays vhdl-modules vhdl-code nexys4ddr fpga-programming

Updated Feb 23, 2021
VHDL

shinesunnysom / Biofeedback-Game-System

CECS 490A/490B Course; Senior Project Design

verilog xilinx xilinx-fpga nexys4ddr

Updated Jul 14, 2021
Verilog

davismariotti / HelicopterGame

A helicopter game written for the Nexys 4 DDR Board in VHDL

vhdl helicopter-game nexys4ddr digital-logic-design

Updated Dec 13, 2017
VHDL

cesar-avalos3 / ROM_Controller

Nexys 4 DDR - Rom Controller

flash fpga vhdl spi rom nexys4ddr

Updated May 1, 2018
VHDL

Elon-Wang / Breakout

Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.

fpga vhdl vivado xilinx-fpga nexys4ddr

Updated May 27, 2019
VHDL

iBug / Nexys4-DDR-stopwatch

A stopwatch on Digilent Nexys4 DDR written in Verilog

fpga verilog vivado nexys4ddr

Updated Nov 28, 2018
VHDL

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