⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

x mega menu is repsonsive mega menu based on vannilajs

Tree Select jQuery plugin

Responsive vertical navigation menu

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Gatery, a library for circuit design.

The Repository contains the code of various Digital Circuits

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

Template project for using gatery

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022

This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime

BDD Gherkin implementation in native SystemVerilog, based on UVM.

probable journey of RTL coding ft. Chandra Prakash