The VHDL programming language was used to construct a simple ALU. This was the last of 4 practicals for CCE1013: Computer Logic 1, a course forming part of my B.Sc. in Computer Science.
The Arithmetic Logic Unit created can be seen below.
ALU sketch
To achieve the creation of a fully functioning ALU, 4 practical sessions were required for the proper exposure and understanding of VHDL (in relation to circuit programming).
These practicals aimed to fulfill the following:
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Practical 1:
- Familiarisation with the Xilinx ISE Design Suite.
- Simulation of simple combinational circuits.
- Observation of Static and Dynamic hazards in signals.
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Practical 2:
- Building and testing a Carry-Ripple adder.
- Building and testing a Carry-Lookahead adder.
- Comparing both adders using propagation delay.
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Practical 3:
- Investigating the difference between signed and unsigned multipliers.
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Practical 4:
- Using the knowledge obtained from past practicals to design and implement a simple ALU having the following inputs and outputs.
Inputs and Ouputs of the ALU created
Individual reports for every practical session can be found here.
Each sub-directory contains a report titled Assignment_SPECIFICATION.pdf, which describes the design process requirements for the chosen practical.
Another report titled DOCUMENTATION.pdf was also included for a detailed technical documentation of the source code.