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Fix LPDDR5; update tests
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@gutodelazeri
gutodelazeri committed Nov 10, 2022
1 parent 5a299e8 commit 88be8a0
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Showing 10 changed files with 40 additions and 23 deletions.
2 changes: 2 additions & 0 deletions .gitignore
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Expand Up @@ -43,3 +43,5 @@ build*/
bin/
*.swp
.~*
cmake-build-debug
cmake-build-release
19 changes: 9 additions & 10 deletions src/DRAMPower/DRAMPower/standards/lpddr5/calculation_LPDDR5.cpp
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Expand Up @@ -79,16 +79,15 @@ namespace DRAMPower {
auto IBeta = dram.memSpec.memPowerSpec[vd].iBeta;

auto I_rho = rho * (IDD3N - IDD2N) + IDD2N;
auto I_1 = (1.0 / B) * (IDD3N + (B - 1) * (rho * (IDD3N - IDD2N) + IDD2N));
auto I_2 = I_1 + (I_1 - I_rho);
auto I_2 = IDD3N + (IDD3N - I_rho);
auto I_theta = (IDD_0 * (t_RP + t_RAS) - IBeta * t_RP) * (1 / t_RAS);
auto IDD5PB_B = (IDD5PB * (t_REFI / 8) - IDD2N * ((t_REFI / 8) - t_RFCPB)) * (1.0 / t_RFCPB);
auto approx_IDD3N = I_rho + B * (I_1 - I_rho);
auto approx_IDD3N = I_rho + B * (IDD3N - I_rho);

for (std::size_t b = 0; b < dram.memSpec.numberOfBanks; ++b) {
const auto &bank = stats.bank[b];

energy.bank_energy[b].E_act += E_act(VDD, I_theta, I_1, t_RAS, bank.counter.act);
energy.bank_energy[b].E_act += E_act(VDD, I_theta, IDD3N, t_RAS, bank.counter.act);
energy.bank_energy[b].E_pre += E_pre(VDD, IBeta, IDD2N, t_RP, bank.counter.pre);
energy.bank_energy[b].E_bg_act += E_BG_act_star(B, VDD, approx_IDD3N, I_rho,stats.bank[b].cycles.activeTime() * t_CK);
energy.bank_energy[b].E_bg_pre += E_BG_pre(B, VDD, IDD2N, stats.total.cycles.pre * t_CK);
Expand All @@ -98,15 +97,15 @@ namespace DRAMPower {
energy.bank_energy[b].E_RDA += E_RD(VDD, IDD4R, I_2, BL, DR, t_WCK, bank.counter.readAuto);
energy.bank_energy[b].E_WRA += E_WR(VDD, IDD4W, I_2, BL, DR, t_WCK, bank.counter.writeAuto);
} else {
energy.bank_energy[b].E_RD += E_RD(VDD, IDD4R, I_1, BL, DR, t_WCK, bank.counter.reads);
energy.bank_energy[b].E_WR += E_WR(VDD, IDD4W, I_1, BL, DR, t_WCK, bank.counter.writes);
energy.bank_energy[b].E_RDA += E_RD(VDD, IDD4R, I_1, BL, DR, t_WCK, bank.counter.readAuto);
energy.bank_energy[b].E_WRA += E_WR(VDD, IDD4W, I_1, BL, DR, t_WCK, bank.counter.writeAuto);
energy.bank_energy[b].E_RD += E_RD(VDD, IDD4R, IDD3N, BL, DR, t_WCK, bank.counter.reads);
energy.bank_energy[b].E_WR += E_WR(VDD, IDD4W, IDD3N, BL, DR, t_WCK, bank.counter.writes);
energy.bank_energy[b].E_RDA += E_RD(VDD, IDD4R, IDD3N, BL, DR, t_WCK, bank.counter.readAuto);
energy.bank_energy[b].E_WRA += E_WR(VDD, IDD4W, IDD3N, BL, DR, t_WCK, bank.counter.writeAuto);
}
energy.bank_energy[b].E_pre_RDA += E_pre(VDD, IBeta, IDD2N, t_RP, bank.counter.readAuto);
energy.bank_energy[b].E_pre_WRA += E_pre(VDD, IBeta, IDD2N, t_RP, bank.counter.writeAuto);
energy.bank_energy[b].E_ref_AB += E_ref_ab(B, VDD, IDD5, IDD3N, t_RFC, bank.counter.refAllBank);
energy.bank_energy[b].E_ref_PB += E_ref_pb(VDD, IDD5PB_B, I_1, t_RFCPB, bank.counter.refPerBank);
energy.bank_energy[b].E_ref_AB += E_ref_ab(B, VDD, IDD5, approx_IDD3N, t_RFC, bank.counter.refAllBank);
energy.bank_energy[b].E_ref_PB += E_ref_pb(VDD, IDD5PB_B, IDD3N, t_RFCPB, bank.counter.refPerBank);
energy.bank_energy[b].E_ref_2B += E_ref_p2b(VDD, IDD5PB_B, I_2, t_RFCPB, bank.counter.refPerTwoBanks);
}

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6 changes: 4 additions & 2 deletions tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_14.cpp
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Expand Up @@ -41,8 +41,10 @@ class DramPowerTest_LPDDR5_14 : public ::testing::Test {
memSpec.numberOfBanks = 8;
memSpec.banksPerGroup = 8;
memSpec.numberOfBankGroups = 1;

memSpec.memTimingSpec.tRAS = 20;
memSpec.BGroupMode = false;


memSpec.memTimingSpec.tRAS = 20;
memSpec.memTimingSpec.tRTP = 10;
memSpec.memTimingSpec.tWR = 11;
memSpec.memTimingSpec.tWL = 0;
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6 changes: 4 additions & 2 deletions tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_15.cpp
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Expand Up @@ -35,8 +35,10 @@ class DramPowerTest_LPDDR5_15 : public ::testing::Test {
memSpec.numberOfBanks = 8;
memSpec.banksPerGroup = 8;
memSpec.numberOfBankGroups = 1;

memSpec.memTimingSpec.tRAS = 10;
memSpec.BGroupMode = false;


memSpec.memTimingSpec.tRAS = 10;
memSpec.memTimingSpec.tRTP = 10;
memSpec.memTimingSpec.tWR = 20;

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6 changes: 4 additions & 2 deletions tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_16.cpp
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Expand Up @@ -37,8 +37,10 @@ class DramPowerTest_LPDDR5_16 : public ::testing::Test {
memSpec.numberOfBanks = 8;
memSpec.banksPerGroup = 8;
memSpec.numberOfBankGroups = 1;

memSpec.memTimingSpec.tRAS = 10;
memSpec.BGroupMode = false;


memSpec.memTimingSpec.tRAS = 10;
memSpec.memTimingSpec.tRTP = 10;
memSpec.memTimingSpec.tRFCPB = 25;
memSpec.memTimingSpec.tWR = 20;
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6 changes: 4 additions & 2 deletions tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_17.cpp
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Expand Up @@ -31,8 +31,10 @@ class DramPowerTest_LPDDR5_17 : public ::testing::Test {
memSpec.numberOfBanks = 8;
memSpec.numberOfBankGroups = 2;
memSpec.perTwoBankOffset = 2;

memSpec.memTimingSpec.tRAS = 10;
memSpec.BGroupMode = true;


memSpec.memTimingSpec.tRAS = 10;
memSpec.memTimingSpec.tRTP = 10;
memSpec.memTimingSpec.tRFCPB = 25;

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4 changes: 3 additions & 1 deletion tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_18.cpp
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Expand Up @@ -34,8 +34,10 @@ class DramPowerTest_LPDDR5_18 : public ::testing::Test {
memSpec.numberOfBankGroups = 2;
memSpec.banksPerGroup = 4;
memSpec.perTwoBankOffset = 2;
memSpec.BGroupMode = true;

memSpec.memTimingSpec.tRAS = 10;

memSpec.memTimingSpec.tRAS = 10;
memSpec.memTimingSpec.tRTP = 10;
memSpec.memTimingSpec.tRCD = 20;
memSpec.memTimingSpec.tRFC = 25;
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6 changes: 4 additions & 2 deletions tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_19.cpp
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Expand Up @@ -34,8 +34,10 @@ class DramPowerTest_LPDDR5_19 : public ::testing::Test {
memSpec.numberOfBanks = 8;
memSpec.numberOfBankGroups = 2;
memSpec.banksPerGroup = 4;

memSpec.memTimingSpec.tRAS = 10;
memSpec.BGroupMode = true;


memSpec.memTimingSpec.tRAS = 10;
memSpec.memTimingSpec.tRTP = 10;
memSpec.memTimingSpec.tRCD = 20;
memSpec.memTimingSpec.tRFC = 25;
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6 changes: 4 additions & 2 deletions tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_20.cpp
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Expand Up @@ -32,8 +32,10 @@ class DramPowerTest_LPDDR5_20 : public ::testing::Test {
memSpec.numberOfBanks = 8;
memSpec.numberOfBankGroups = 2;
memSpec.banksPerGroup = 4;

memSpec.memTimingSpec.tRAS = 10;
memSpec.BGroupMode = true;


memSpec.memTimingSpec.tRAS = 10;
memSpec.memTimingSpec.tRTP = 10;
memSpec.memTimingSpec.tRCD = 20;
memSpec.memTimingSpec.tRFC = 25;
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2 changes: 2 additions & 0 deletions tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_21.cpp
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Expand Up @@ -33,6 +33,8 @@ class DramPowerTest_LPDDR5_21 : public ::testing::Test {
memSpec.numberOfBanks = 8;
memSpec.numberOfBankGroups = 2;
memSpec.banksPerGroup = 4;
memSpec.BGroupMode = true;


memSpec.memTimingSpec.tRAS = 10;
memSpec.memTimingSpec.tRTP = 10;
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