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Merge pull request #49 from tukl-msd/master
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Power of individual banks
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@Sv3n
Sv3n authored Oct 30, 2016
2 parents e18a37f + 767cb37 commit 90d6290
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1 change: 1 addition & 0 deletions .gitignore
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Expand Up @@ -15,3 +15,4 @@ traces.zip
cscope.*
commands.trace
coverage_report
.DS_Store
4 changes: 2 additions & 2 deletions Makefile
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Expand Up @@ -55,8 +55,8 @@ LIBSOURCES := $(wildcard src/libdrampower/*.cc) \
src/MemPowerSpec.cc\
src/MemTimingSpec.cc\
src/Parameter.cc\
src/Parametrisable.cc

src/Parametrisable.cc\
src/MemBankWiseParams.cc

XMLPARSERSOURCES := $(wildcard src/xmlparser/*.cc)
ALLSOURCES := $(wildcard src/cli/*.cc) $(wildcard src/*.cc) $(wildcard src/xmlparser/*.cc) $(wildcard src/libdrampower/*.cc)
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12 changes: 6 additions & 6 deletions README.md
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Expand Up @@ -10,7 +10,7 @@ The master branch of the repository should be regarded as the bleeding-edge vers

## 1. Installation

Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. src/cli/drampower.cc file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use:
Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. [drampower.cc](src/cli/drampower.cc) file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use:
```bash
make -j4
```
Expand All @@ -36,7 +36,7 @@ An example is given in ```traces/commands.trace```

The format it uses is: ```<timestamp>,<command>,<bank>```.
For example, "500,ACT,2", where ACT is the command and 2 is the bank. Timestamp is in clock cycles (cc), the list of supported commands is
mentioned in src/MemCommand.h and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be
mentioned in [MemCommand.h](src/MemCommand.h) and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be
specified. The timing correctness of the trace is not verified by the tool and is assumed to be accurate. However, warning messages are provided, to identify if the memory or bank state is inconsistent in the trace. A sample command trace is provided in the traces/ folder.

### Transaction Traces
Expand All @@ -53,7 +53,7 @@ Four sample MediaBench application transaction traces have been provided. The Me

## 5. Usage

src/cli/drampower.cc is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes.
[drampower.cc](src/cli/drampower.cc) is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes.

To use DRAMPower at the command-level (command trace), after make, use the following:
```bash
Expand Down Expand Up @@ -108,7 +108,7 @@ To include these XMLs in your simulations, simply use them as the target memory.
## 8. Example Usage

An example of using this tool is provided below. To compile the example,
use the Makefile and make sure the Gcc and Xerces-c are installed. Then, run:
use the Makefile and make sure the gcc and Xerces-c are installed. Then, run:
```
make -j4
```
Expand Down Expand Up @@ -204,9 +204,9 @@ It also reports the simulation start/end times and the total simulation time in
## 9. DRAMPower Library

The DRAMPower tool has an additional feature and can be used as a library.
In order to use the library run "make lib", include src/libdrampower/LibDRAMPower.h in your project and
In order to use the library run "make lib", include [LibDRAMPower.h](src/libdrampower/LibDRAMPower.h) in your project and
link the file src/libdrampower.a with your project.
Two examples for the usage of the library can be found in the folder test/libdrampowertest:lib_test.cc and window_example.cc
Examples for the usage of the library are [lib_test.cc](test/libdrampowertest/lib_test.cc) and [window_example.cc](test/libdrampowertest/window_example.cc).

## 10. Authors & Acknowledgment

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55 changes: 55 additions & 0 deletions memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml
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@@ -0,0 +1,55 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>

<parameter id="memoryId" type="string" value="SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit" />
<parameter id="memoryType" type="string" value="DDR3" />
<memarchitecturespec>
<parameter id="width" type="uint" value="16" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="800" />
<parameter id="RC" type="uint" value="39" />
<parameter id="RCD" type="uint" value="11" />
<parameter id="RL" type="uint" value="11" />
<parameter id="RP" type="uint" value="11" />
<parameter id="RFC" type="uint" value="88" />
<parameter id="RAS" type="uint" value="28" />
<parameter id="WL" type="uint" value="8" />
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="0" />
<parameter id="RTP" type="uint" value="6" />
<parameter id="WR" type="uint" value="12" />
<parameter id="XP" type="uint" value="5" />
<parameter id="XPDLL" type="uint" value="20" />
<parameter id="XS" type="uint" value="96" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="REFI" type="uint" value="6240" />
<parameter id="CL" type="uint" value="11" />
<parameter id="FAW" type="uint" value="32" />
<parameter id="RRD" type="uint" value="6" />
<parameter id="CCD" type="uint" value="4" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="CKE" type="uint" value="4" />
<parameter id="CKESR" type="uint" value="5" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="75.0" />
<parameter id="idd2p0" type="double" value="10.0" />
<parameter id="idd2p1" type="double" value="25.0" />
<parameter id="idd2n" type="double" value="40.0" />
<parameter id="idd3p0" type="double" value="40.0" />
<parameter id="idd3p1" type="double" value="40.0" />
<parameter id="idd3n" type="double" value="55.0" />
<parameter id="idd4w" type="double" value="190.0" />
<parameter id="idd4r" type="double" value="180.0" />
<parameter id="idd5" type="double" value="170.0" />
<parameter id="idd6" type="double" value="10.0" />
<parameter id="vdd" type="double" value="1.5" />
</mempowerspec>
</memspec>
57 changes: 57 additions & 0 deletions memspecs/modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml
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@@ -0,0 +1,57 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>

<parameter id="memoryId" type="string" value="MICRON_1Gb_DDR3-1600_8bit_G_3s" />
<parameter id="memoryType" type="string" value="DDR3" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="16384" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="800" />
<parameter id="RC" type="uint" value="38" />
<parameter id="RCD" type="uint" value="10" />
<parameter id="RL" type="uint" value="10" />
<parameter id="RP" type="uint" value="10" />
<parameter id="RFC" type="uint" value="88" />
<parameter id="REFB" type="uint" value="38" /><!-- Manually added := RAS + RP -->
<parameter id="RAS" type="uint" value="28" />
<parameter id="WL" type="uint" value="8" />
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="0" />
<parameter id="RTP" type="uint" value="6" />
<parameter id="WR" type="uint" value="12" />
<parameter id="XP" type="uint" value="6" />
<parameter id="XPDLL" type="uint" value="20" />
<parameter id="XS" type="uint" value="96" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="REFI" type="uint" value="6240" />
<parameter id="CL" type="uint" value="10" />
<parameter id="FAW" type="uint" value="24" />
<parameter id="RRD" type="uint" value="5" />
<parameter id="CCD" type="uint" value="4" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="4" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="66.79" />
<parameter id="idd2p0" type="double" value="10.04" />
<parameter id="idd2p1" type="double" value="25.12" />
<parameter id="idd2n" type="double" value="41.67" />
<parameter id="idd3p0" type="double" value="32.44" />
<parameter id="idd3p1" type="double" value="32.44" />
<parameter id="idd3n" type="double" value="41.71" />
<parameter id="idd4w" type="double" value="135.11" />
<parameter id="idd4r" type="double" value="131.66" />
<parameter id="idd5" type="double" value="162.85" />
<parameter id="idd5B" type="double" value="25.08" /> <!-- Manually added := (idd0 - idd3n) -->
<parameter id="idd6" type="double" value="6.68" />
<parameter id="vdd" type="double" value="1.5" />
</mempowerspec>
</memspec>
65 changes: 56 additions & 9 deletions src/CmdHandlers.cc
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Expand Up @@ -63,7 +63,7 @@ void CommandAnalysis::handleAct(unsigned bank, int64_t timestamp)
// If the bank is already active ignore the command and generate a
// warning.
if (isPrecharged(bank)) {
numberofacts++;
numberofactsBanks[bank]++;

if (nActiveBanks() == 0) {
// Here a memory state transition to ACT is happening. Save the
Expand All @@ -88,7 +88,7 @@ void CommandAnalysis::handleRd(unsigned bank, int64_t timestamp)
if (isPrecharged(bank)) {
printWarning("Bank is not active!", MemCommand::RD, timestamp, bank);
}
numberofreads++;
numberofreadsBanks[bank]++;
idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp);
latest_read_cycle = timestamp;
}
Expand All @@ -101,7 +101,7 @@ void CommandAnalysis::handleWr(unsigned bank, int64_t timestamp)
if (isPrecharged(bank)) {
printWarning("Bank is not active!", MemCommand::WR, timestamp, bank);
}
numberofwrites++;
numberofwritesBanks[bank]++;
idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp);
latest_write_cycle = timestamp;
}
Expand All @@ -118,15 +118,37 @@ void CommandAnalysis::handleRef(unsigned bank, int64_t timestamp)
numberofrefs++;
idle_pre_update(timestamp, latest_pre_cycle);
first_act_cycle = timestamp;
std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp);
precycles += zero_guard(timestamp - last_pre_cycle, "2 last_pre_cycle is in the future.");
last_pre_cycle = timestamp + memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP;
latest_pre_cycle = last_pre_cycle;
actcycles += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP;
for (auto &e : actcyclesBanks) {
e += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP;
}
for (auto& bs : bank_state) {
bs = BANK_PRECHARGED;
}
}

void CommandAnalysis::handleRefB(unsigned bank, int64_t timestamp)
{
// A REFB command requires a previous PRE command.
if (isPrecharged(bank)) {
// This previous PRE command handler is also responsible for keeping the
// memory state updated.
// Here we consider that the memory state is not changed in order to keep
// things simple, since the transition from PRE to ACT state takes time.
numberofrefbBanks[bank]++;
// Length of the refresh: here we have an approximation, we consider tRP
// also as act cycles because the bank will be precharged (stable) after
// tRP.
actcyclesBanks[bank] += memSpec.memTimingSpec.RAS + memSpec.memTimingSpec.RP;
} else {
printWarning("Bank must be precharged for REFB!", MemCommand::REFB, timestamp, bank);
}
}

void CommandAnalysis::handlePre(unsigned bank, int64_t timestamp)
{
printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::PRE, timestamp, bank);
Expand All @@ -140,7 +162,8 @@ void CommandAnalysis::handlePre(unsigned bank, int64_t timestamp)

// Precharge only if the target bank is active
if (bank_state[bank] == BANK_ACTIVE) {
numberofpres++;
numberofpresBanks[bank]++;
actcyclesBanks[bank] += zero_guard(timestamp - first_act_cycle_banks[bank], "first_act_cycle is in the future (bank).");
// Since we got here, at least one bank is active
assert(nActiveBanks() != 0);

Expand Down Expand Up @@ -169,17 +192,25 @@ void CommandAnalysis::handlePreA(unsigned bank, int64_t timestamp)
// which the memory state changes from ACT to PRE, aka last_pre_cycle).
// Calculate the number of active cycles if the memory was in the
// active state before, but there is a state transition to PRE now.

if (nActiveBanks() > 0) {
// Active banks are being precharged
numberofpres += nActiveBanks();
// At least one bank was active, therefore the current memory state is
// ACT. Since all banks are being precharged a memory state transition
// to PRE is happening. Add to the counter the amount of cycles the
// memory remained in the ACT state.

actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future.");
last_pre_cycle = timestamp;

for (unsigned b = 0; b < num_banks; b++) {
if (bank_state[b] == BANK_ACTIVE) {
// Active banks are being precharged
numberofpresBanks[b] += 1;
actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank).");
}
}

idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp);

latest_pre_cycle = timestamp;
Expand All @@ -204,6 +235,11 @@ void CommandAnalysis::handlePdnFAct(unsigned bank, int64_t timestamp)
last_bank_state = bank_state;
pdn_cycle = timestamp;
actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future.");
for (unsigned b = 0; b < num_banks; b++) {
if (bank_state[b] == BANK_ACTIVE) {
actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank).");
}
}
idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp);
mem_state = CommandAnalysis::MS_PDN_F_ACT;
}
Expand All @@ -220,6 +256,11 @@ void CommandAnalysis::handlePdnSAct(unsigned bank, int64_t timestamp)
last_bank_state = bank_state;
pdn_cycle = timestamp;
actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future.");
for (unsigned b = 0; b < num_banks; b++) {
if (bank_state[b] == BANK_ACTIVE) {
actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank).");
}
}
idle_act_update(latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp);
mem_state = CommandAnalysis::MS_PDN_S_ACT;
}
Expand Down Expand Up @@ -280,6 +321,7 @@ void CommandAnalysis::handlePupAct(int64_t timestamp)
mem_state = MS_NOT_IN_PD;
bank_state = last_bank_state;
first_act_cycle = timestamp;
std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp);
}

void CommandAnalysis::handlePupPre(int64_t timestamp)
Expand Down Expand Up @@ -318,7 +360,7 @@ void CommandAnalysis::handleSREn(unsigned bank, int64_t timestamp)
sref_cycle = timestamp;
sref_cycle_window = timestamp;
sref_ref_pre_cycles_window = 0;
sref_ref_act_cycles_window = 0;
sref_ref_act_cycles_window = 0;
precycles += zero_guard(timestamp - last_pre_cycle, "5 last_pre_cycle is in the future.");
idle_pre_update(timestamp, latest_pre_cycle);
mem_state = CommandAnalysis::MS_SREF;
Expand Down Expand Up @@ -530,6 +572,11 @@ void CommandAnalysis::handleNopEnd(int64_t timestamp)
// May be optionally used at the end of memory trace for better accuracy
// Update all counters based on completion of operations.
const MemTimingSpec& t = memSpec.memTimingSpec;
for (unsigned b = 0; b < num_banks; b++) {
if (bank_state[b] == BANK_ACTIVE) {
actcyclesBanks[b] += zero_guard(timestamp - first_act_cycle_banks[b], "first_act_cycle is in the future (bank)");
}
}

if (nActiveBanks() > 0 && mem_state == MS_NOT_IN_PD) {
actcycles += zero_guard(timestamp - first_act_cycle, "first_act_cycle is in the future");
Expand Down Expand Up @@ -562,7 +609,7 @@ void CommandAnalysis::handleNopEnd(int64_t timestamp)
}
sref_cycles += zero_guard(timestamp - sref_cycle_window, "sref_cycle_window is in the future");
} else if (timestamp > sref_cycle + rfc_minus_rp) {

if (sref_cycle_window <= sref_cycle + rfc_minus_rp) {
sref_ref_act_cycles += rfc_minus_rp - sref_ref_act_cycles_window;
sref_ref_act_cycles_window = rfc_minus_rp;
Expand All @@ -575,4 +622,4 @@ void CommandAnalysis::handleNopEnd(int64_t timestamp)
sref_ref_act_cycles += timestamp - sref_cycle_window;
}
}
}
}
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