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Set the module name for many parameterized modules with chisel's desiredName #83

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merged 1 commit into from
Jun 5, 2024
Merged

Set the module name for many parameterized modules with chisel's desiredName #83

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3 changes: 3 additions & 0 deletions hardfloat/src/main/scala/DivSqrtRecFN_small.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -199,6 +199,7 @@ class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
Expand Down Expand Up @@ -421,6 +422,7 @@ class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
Expand Down Expand Up @@ -466,6 +468,7 @@ class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
Expand Down
1 change: 1 addition & 0 deletions hardfloat/src/main/scala/INToRecFN.scala
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Expand Up @@ -42,6 +42,7 @@ import consts._

class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
Expand Down
3 changes: 3 additions & 0 deletions hardfloat/src/main/scala/MulAddRecFN.scala
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Expand Up @@ -70,6 +70,7 @@ class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
Expand Down Expand Up @@ -167,6 +168,7 @@ class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
Expand Down Expand Up @@ -297,6 +299,7 @@ class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule

class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
Expand Down
1 change: 1 addition & 0 deletions hardfloat/src/main/scala/RecFNToIN.scala
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Expand Up @@ -45,6 +45,7 @@ import consts._

class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
Expand Down
2 changes: 2 additions & 0 deletions hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala
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Expand Up @@ -54,6 +54,7 @@ class
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
Expand Down Expand Up @@ -294,6 +295,7 @@ class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
Expand Down
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