Skip to content

Commit

Permalink
Initial commit
Browse files Browse the repository at this point in the history
  • Loading branch information
mcbridejc committed Mar 2, 2022
0 parents commit c2f94f1
Show file tree
Hide file tree
Showing 32 changed files with 77,478 additions and 0 deletions.
29 changes: 29 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
PurpleDrop 50x75mm Top Plate Frame
==================================

Frame kit for building drop surfaces on PurpleDrop with 50x75mm top plate.

The kit comes in two parts:

- The "frame" holds the PET film dielectric, and locates the glass plate
- The "cover" is screwed on to hold the top plate in place, and make electrical contact to it.

Each part is designed as PCB in KiCad, and can be built at any PCB manufacturer using the gerber files attached in releases.

# Parts

Two COTS parts are added to the cover:

- Conductive gasket - [Laird Technologies 4245PA51H01800](https://www.digikey.com/en/products/detail/laird-technologies-emi/4245PA51H01800/2175938) - A 1mm thick, 3mm wide strip of foam gasket in conductive fabric. This serves to create pressure on the top plate, and to make contact to the ITO coating via copper tape.
- Header pin - A single, right angle header, like [Sullins GBC01SBSN-M89](https://www.digikey.com/en/products/detail/sullins-connector-solutions/GBC01SBSN-M89/862318) or similar

# Dimensions

## Frame

![Frame Dimensions](/docs/frame_50x75_dimensions.png?raw=true "Frame Dimensions")

## Cover

![Cover Dimensions](/docs/cover_50x75_dimensions.png?raw=true "Cover Dimensions")

21 changes: 21 additions & 0 deletions cover/cover_50x75-cache.lib
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_01x01
#
DEF Connector_Generic_Conn_01x01 J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "Connector_Generic_Conn_01x01" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 5 0 -5 1 1 6 N
S -50 50 50 -50 1 1 10 f
X Pin_1 1 -200 0 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library
416 changes: 416 additions & 0 deletions cover/cover_50x75.kicad_pcb

Large diffs are not rendered by default.

180 changes: 180 additions & 0 deletions cover/cover_50x75.kicad_pro
Original file line number Diff line number Diff line change
@@ -0,0 +1,180 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 2.5,
"height": 2.5,
"width": 2.5
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": true,
"min_clearance": 0.3
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.09999999999999999,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"use_height_for_length_calcs": true
},
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "cover_50x75.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"label_size_ratio": 0.25,
"pin_symbol_size": 0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}
16 changes: 16 additions & 0 deletions cover/cover_50x75.pretty/Header1_RA.kicad_mod
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
(module Header1_RA (layer F.Cu) (tedit 60353B81)
(fp_text reference REF** (at 0 5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Header1_RA (at 0 3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.9 0) (end -9.5 0) (layer F.SilkS) (width 0.25))
(fp_line (start -3.5 -0.6) (end -3.5 0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -3.5 0.6) (end -5.9 0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -5.9 0.6) (end -5.9 -0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -5.9 -0.6) (end -3.5 -0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -3.5 -0.6) (end -3.5 -0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -3.5 0) (end -1.6 0) (layer F.SilkS) (width 0.25))
(pad 1 smd rect (at 0 0) (size 2 1.2) (layers F.Cu F.Paste F.Mask))
)
28 changes: 28 additions & 0 deletions cover/cover_50x75.sch
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_01x01 J1
U 1 1 608C4740
P 5500 3100
F 0 "J1" H 5580 3142 50 0000 L CNN
F 1 "Conn_01x01" H 5580 3051 50 0000 L CNN
F 2 "cover_50x75:Header1_RA" H 5500 3100 50 0001 C CNN
F 3 "~" H 5500 3100 50 0001 C CNN
F 4 "GBC01SBSN-M89" H 5500 3100 50 0001 C CNN "Mfg Part Number"
1 5500 3100
1 0 0 -1
$EndComp
$EndSCHEMATC
1 change: 1 addition & 0 deletions cover/fp-info-cache
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
0
3 changes: 3 additions & 0 deletions cover/fp-lib-table
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
(fp_lib_table
(lib (name cover_50x75)(type KiCad)(uri ${KIPRJMOD}/cover_50x75.pretty)(options "")(descr ""))
)
61 changes: 61 additions & 0 deletions cover/gerbers/cover_50x75-B_Cu.gbr
Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
%TF.GenerationSoftware,KiCad,Pcbnew,6.0.2-378541a8eb~116~ubuntu21.10.1*%
%TF.CreationDate,2022-03-01T19:57:36-08:00*%
%TF.ProjectId,cover_50x75,636f7665-725f-4353-9078-37352e6b6963,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Copper,L2,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 6.0.2-378541a8eb~116~ubuntu21.10.1) date 2022-03-01 19:57:36*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%TA.AperFunction,NonConductor*%
%ADD10C,0.100000*%
%TD*%
%TA.AperFunction,ViaPad*%
%ADD11C,0.800000*%
%TD*%
%TA.AperFunction,Conductor*%
%ADD12C,0.600000*%
%TD*%
G04 APERTURE END LIST*
D10*
X203270000Y-56840000D02*
X173270000Y-56840000D01*
X173270000Y-56840000D02*
X173270000Y-53840000D01*
X173270000Y-53840000D02*
X203270000Y-53840000D01*
X203270000Y-53840000D02*
X203270000Y-56840000D01*
G36*
X203270000Y-56840000D02*
G01*
X173270000Y-56840000D01*
X173270000Y-53840000D01*
X203270000Y-53840000D01*
X203270000Y-56840000D01*
G37*
X203270000Y-56840000D02*
X173270000Y-56840000D01*
X173270000Y-53840000D01*
X203270000Y-53840000D01*
X203270000Y-56840000D01*
D11*
%TO.N,*%
X214520000Y-54210000D03*
X214570000Y-55560000D03*
X212020000Y-55610000D03*
X212020000Y-54210000D03*
X213270000Y-52960000D03*
%TD*%
D12*
%TO.N,*%
X202850000Y-55610000D02*
X202500000Y-55260000D01*
X212020000Y-55610000D02*
X202850000Y-55610000D01*
%TD*%
M02*
Loading

0 comments on commit c2f94f1

Please sign in to comment.