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SM-10: Integrate FCCU support.
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Signed-off-by: Chuck Cannon <[email protected]>
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@cecannon7
cecannon7 committed Jan 19, 2024
1 parent a42b8f6 commit e41bbe1
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Showing 58 changed files with 90,140 additions and 56 deletions.
50 changes: 43 additions & 7 deletions boards/mcimx95evk/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
#include "fsl_systick.h"
#include "fsl_wdog32.h"
#include "fsl_cache.h"
#include "fsl_iomuxc.h"

/*******************************************************************************
* Definitions
Expand All @@ -29,14 +30,14 @@
#define BOARD_SYSTICK_CLK_ROOT CLOCK_ROOT_M33SYSTICK /* Dedicated CCM root */

/* SM WDOG */
#define BOARD_WDOG_BASE_PTR WDOG1
#define BOARD_WDOG_IRQn WDOG1_IRQn
#define BOARD_WDOG_BASE_PTR WDOG2
#define BOARD_WDOG_IRQn WDOG2_IRQn
#define BOARD_WDOG_CLK_SRC kWDOG32_ClockSource1 /* lpo_clk @ 32K */
#define BOARD_WDOG_TIMEOUT 0xFFFFU /* 65535 ticks @ 32K = 2 sec */
#define BOARD_WDOG_SRMASK (1UL << RST_REASON_WDOG1)
#define BOARD_WDOG_ANY_INIT ~(BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_MASK)
#define BOARD_WDOG_ANY_MASK BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_MASK
#define BOARD_WDOG_IPG_DEBUG BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_WDOG1_MASK
#define BOARD_WDOG_SRMASK (1UL << RST_REASON_WDOG2)
#define BOARD_WDOG_ANY_INIT ~(BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK)
#define BOARD_WDOG_ANY_MASK BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK
#define BOARD_WDOG_IPG_DEBUG BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_WDOG2_MASK

/* SM handlers configuration */
#define BOARD_HANDLER_PRIO_PREEMPT_CRITICAL 0U // Highest premptive
Expand Down Expand Up @@ -313,6 +314,11 @@ void BOARD_InitHandlers(void)
NVIC_EnableIRQ(ELE_Group2_IRQn);
NVIC_EnableIRQ(ELE_Group3_IRQn);

/* Enable FCCU handler */
NVIC_EnableIRQ(FCCU0_IRQn);
NVIC_EnableIRQ(FCCU1_IRQn);
NVIC_EnableIRQ(FCCU2_IRQn);

/* Enable GPIO1 handler */
NVIC_EnableIRQ(GPIO1_0_IRQn);
}
Expand Down Expand Up @@ -346,11 +352,13 @@ void BOARD_InitTimers(void)
wdogConfig.enableInterrupt = true;
WDOG32_Init(BOARD_WDOG_BASE_PTR, &wdogConfig);
NVIC_SetPriority(BOARD_WDOG_IRQn, BOARD_HANDLER_PRIO_PREEMPT_CRITICAL);
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Configure to just non-FCCU SM watchdogs */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK = BOARD_WDOG_ANY_INIT;

/* Switch WDOG to COLD mode */
BOARD_WdogModeSet(BOARD_WDOG_MODE_COLD);

/* Halt SM WDOG on M33 debug entry */
BLK_CTRL_NS_AONMIX->IPG_DEBUG_CM33 = (BOARD_WDOG_IPG_DEBUG);

Expand All @@ -370,29 +378,57 @@ void BOARD_WdogModeSet(uint32_t mode)
/* Allow WDOG to generate internal warm reset */
SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK);

/* Enable WDOG interrupt */
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Disable WDOG_ANY */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK;

/* Drive WDOG_ANY from WDOG */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
break;
case BOARD_WDOG_MODE_COLD: /* cold */
/* Allow WDOG to generate internal warm reset */
SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK);

/* Enable WDOG interrupt */
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Enable WDOG_ANY */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK &= ~BOARD_WDOG_ANY_MASK;

/* Drive WDOG_ANY from WDOG */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
break;
case BOARD_WDOG_MODE_IRQ: /* irq */
/* Enable WDOG interrupt */
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Disallow WDOG to generate internal warm reset */
SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK;

/* Disable WDOG_ANY */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK;

/* Drive WDOG_ANY from WDOG */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
break;
case BOARD_WDOG_MODE_OFF: /* off */
WDOG32_Deinit(BOARD_WDOG_BASE_PTR);
break;
case BOARD_WDOG_MODE_TRIGGER: /* trigger */
BOARD_WDOG_BASE_PTR->CNT = 0U;
break;
case BOARD_WDOG_MODE_FCCU: /* fccu */
/* Drive WDOG_ANY from FCCU */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__FCCU_EOUT1, 0U);

/* Disallow WDOG to generate internal warm reset */
SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK;

/* Disable WDOG interrupt */
NVIC_DisableIRQ(BOARD_WDOG_IRQn);
break;
default:
; /* Intentional empty default */
break;
Expand Down
1 change: 1 addition & 0 deletions boards/mcimx95evk/board.h
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@
#define BOARD_WDOG_MODE_IRQ 2U /*!< Wdog generate IRQ only */
#define BOARD_WDOG_MODE_OFF 3U /*!< Wdog disabled */
#define BOARD_WDOG_MODE_TRIGGER 4U /*!< Trigger wdog */
#define BOARD_WDOG_MODE_FCCU 5U /*!< Wdog generate FCCU fault */
/** @} */

/*******************************************************************************
Expand Down
6 changes: 6 additions & 0 deletions boards/mcimx95evk/sm/brd_sm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -141,6 +141,12 @@ int32_t BRD_SM_Init(int argc, const char * const argv[], uint32_t *mSel)
status = DEV_SM_Init(BOARD_BOOT_LEVEL, BOARD_PERF_LEVEL);
}

if (status == SM_ERR_SUCCESS)
{
/* Switch WDOG to FCCU mode */
BOARD_WdogModeSet(BOARD_WDOG_MODE_FCCU);
}

/* Configure ISO controls based on feature fuses */
uint32_t ipIsoMask = 0U;

Expand Down
36 changes: 35 additions & 1 deletion boards/mcimx95stub/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@
#include "fsl_systick.h"
#include "fsl_wdog32.h"
#include "fsl_cache.h"
#include "fsl_iomuxc.h"

/*******************************************************************************
* Definitions
Expand Down Expand Up @@ -315,6 +316,9 @@ void BOARD_InitHandlers(void)
NVIC_EnableIRQ(ELE_Group1_IRQn);
NVIC_EnableIRQ(ELE_Group2_IRQn);
NVIC_EnableIRQ(ELE_Group3_IRQn);

/* Enable FCCU handler */
NVIC_EnableIRQ(FCCU0_IRQn);
}

/*--------------------------------------------------------------------------*/
Expand Down Expand Up @@ -346,11 +350,13 @@ void BOARD_InitTimers(void)
wdogConfig.enableInterrupt = true;
WDOG32_Init(BOARD_WDOG_BASE_PTR, &wdogConfig);
NVIC_SetPriority(BOARD_WDOG_IRQn, BOARD_HANDLER_PRIO_PREEMPT_CRITICAL);
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Configure to just non-FCCU SM watchdogs */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK = BOARD_WDOG_ANY_INIT;

/* Switch WDOG to COLD mode */
BOARD_WdogModeSet(BOARD_WDOG_MODE_COLD);

/* Halt SM WDOG on M33 debug entry */
BLK_CTRL_NS_AONMIX->IPG_DEBUG_CM33 = (BOARD_WDOG_IPG_DEBUG);

Expand All @@ -370,29 +376,57 @@ void BOARD_WdogModeSet(uint32_t mode)
/* Allow WDOG to generate internal warm reset */
SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK);

/* Enable WDOG interrupt */
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Disable WDOG_ANY */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK;

/* Drive WDOG_ANY from WDOG */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
break;
case BOARD_WDOG_MODE_COLD: /* cold */
/* Allow WDOG to generate internal warm reset */
SRC_GEN->SRMASK &= (~BOARD_WDOG_SRMASK);

/* Enable WDOG interrupt */
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Enable WDOG_ANY */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK &= ~BOARD_WDOG_ANY_MASK;

/* Drive WDOG_ANY from WDOG */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
break;
case BOARD_WDOG_MODE_IRQ: /* irq */
/* Enable WDOG interrupt */
NVIC_EnableIRQ(BOARD_WDOG_IRQn);

/* Disallow WDOG to generate internal warm reset */
SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK;

/* Disable WDOG_ANY */
BLK_CTRL_S_AONMIX->WDOG_ANY_MASK |= BOARD_WDOG_ANY_MASK;

/* Drive WDOG_ANY from WDOG */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__WDOG_ANY, 0U);
break;
case BOARD_WDOG_MODE_OFF: /* off */
WDOG32_Deinit(BOARD_WDOG_BASE_PTR);
break;
case BOARD_WDOG_MODE_TRIGGER: /* trigger */
BOARD_WDOG_BASE_PTR->CNT = 0U;
break;
case BOARD_WDOG_MODE_FCCU: /* fccu */
/* Drive WDOG_ANY from FCCU */
IOMUXC_SetPinMux(IOMUXC_PAD_WDOG_ANY__FCCU_EOUT1, 0U);

/* Disallow WDOG to generate internal warm reset */
SRC_GEN->SRMASK |= BOARD_WDOG_SRMASK;

/* Disable WDOG interrupt */
NVIC_DisableIRQ(BOARD_WDOG_IRQn);
break;
default:
; /* Intentional empty default */
break;
Expand Down
1 change: 1 addition & 0 deletions boards/mcimx95stub/board.h
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@
#define BOARD_WDOG_MODE_IRQ 2U /*!< Wdog generate IRQ only */
#define BOARD_WDOG_MODE_OFF 3U /*!< Wdog disabled */
#define BOARD_WDOG_MODE_TRIGGER 4U /*!< Trigger wdog */
#define BOARD_WDOG_MODE_FCCU 5U /*!< Wdog generate FCCU fault */
/** @} */

/*******************************************************************************
Expand Down
46 changes: 46 additions & 0 deletions components/SAF/SafetyBase/include/MIMX_SAF_Version.h
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Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
/**
* @file MIMX_SAF_Version.h
* @version 0.4.0
*
* @brief MIMX_SAF SafetyBase - Defines the software version of the MIMX_SAF.
* @details The software version defined in this module is used as a reference value for
* file version checks within the MIMX_SAF.
*
* @addtogroup SAFETY_BASE_COMPONENT
* @{
*/
/*==================================================================================================
* Project : MIMX_SAF
* Platform : CORTEXM
*
* SW Version : 0.4.0
* Build Version : IMX95_SAF_0_4_0_CD01_20231113
*
* Copyright 2023 NXP
* Detailed license terms of software usage can be found in the license.txt
* file located in the root folder of this package.
==================================================================================================*/

#ifndef MIMX_SAF_VERSION_H
#define MIMX_SAF_VERSION_H

#ifdef __cplusplus
extern "C"{
#endif


/*==================================================================================================
* MIMX_SAF SOFTWARE VERSION INFORMATION
==================================================================================================*/
#define MIMX_SAF_SW_MAJOR_VERSION 0
#define MIMX_SAF_SW_MINOR_VERSION 4
#define MIMX_SAF_SW_PATCH_VERSION 0


#ifdef __cplusplus
}
#endif

#endif /*MIMX_SAF_VERSION_H*/

/** @} */
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